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Completes the first test stream.
... and improves decoding consistency in conjunction.
This commit is contained in:
Thomas Harte
parent
762ecab3aa
commit
5058a8b96a
@ -37,11 +37,42 @@ namespace {
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XCTAssertEqual(instruction.operation, operation);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination {
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination displacement:(int16_t)displacement {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
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XCTAssertEqual(instruction.source(), source);
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XCTAssertEqual(instruction.destination(), destination);
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XCTAssertEqual(instruction.displacement(), displacement);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination displacement:(int16_t)displacement operand:(uint16_t)operand {
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[self assert:instruction operation:operation size:size source:source destination:destination displacement:displacement];
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XCTAssertEqual(instruction.operand(), operand);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination operand:(uint16_t)operand {
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[self assert:instruction operation:operation size:size source:source destination:destination displacement:0 operand:operand];
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination {
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[self assert:instruction operation:operation size:size source:source destination:destination displacement:0];
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
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XCTAssertEqual(instruction.source(), source);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size destination:(Source)destination {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
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XCTAssertEqual(instruction.destination(), destination);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size operand:(uint16_t)operand destination:(Source)destination {
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@ -50,6 +81,7 @@ namespace {
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XCTAssertEqual(instruction.destination(), destination);
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XCTAssertEqual(instruction.source(), Source::Immediate);
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XCTAssertEqual(instruction.operand(), operand);
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XCTAssertEqual(instruction.displacement(), 0);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation displacement:(int16_t)displacement {
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@ -60,6 +92,7 @@ namespace {
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- (void)assert:(Instruction &)instruction operation:(Operation)operation operand:(uint16_t)operand {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.operand(), operand);
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XCTAssertEqual(instruction.displacement(), 0);
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}
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// MARK: - Decoder
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@ -81,6 +114,7 @@ namespace {
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while(byte != stream.end()) {
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const auto [size, next] = decoder.decode(byte, stream.end() - byte);
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if(size <= 0) break;
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NSLog(@"%@ %@", @(instructions.size()), @(size));
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instructions.push_back(next);
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byte += size;
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}
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@ -122,7 +156,7 @@ namespace {
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// ret
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// lret $0x4826
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// [[ gs insw (%dx),%es:(%di) ]]
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// [[ omitted: gs insw (%dx),%es:(%di) ]]
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// jnp 0xffffffaf
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// ret $0x4265
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[self assert:instructions[4] operation:Operation::RETN];
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@ -139,63 +173,132 @@ namespace {
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[self assert:instructions[10] operation:Operation::JO displacement:0x20];
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[self assert:instructions[11] operation:Operation::XCHG size:2 source:Source::AX destination:Source::SP];
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// (bad)
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// aam $0x93
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// ODA has:
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// c4 (bad)
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// d4 93 aam $0x93
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//
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// That assumes that upon discovering that the d4 doesn't make a valid LES,
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// it can become an instruction byte. I'm not persuaded. So I'm taking:
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//
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// c4 d4 (bad)
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// 93 XCHG AX, BX
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[self assert:instructions[12] operation:Operation::Invalid];
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[self assert:instructions[13] operation:Operation::XCHG size:2 source:Source::AX destination:Source::BX];
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// inc %bx
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// cmp $0x8e,%al
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// [self assert:instructions[12] operation:Operation::Invalid];
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// push $0x65
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// [[ omitted: push $0x65 ]]
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// sbb 0x45(%bx,%si),%bh
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// adc %bh,0x3c(%bx)
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[self assert:instructions[14] operation:Operation::INC size:2 source:Source::BX destination:Source::BX];
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[self assert:instructions[15] operation:Operation::CMP size:1 operand:0x8e destination:Source::AL];
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[self assert:instructions[16] operation:Operation::SBB size:1 source:Source::IndBXPlusSI destination:Source::BH displacement:0x45];
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[self assert:instructions[17] operation:Operation::ADC size:1 source:Source::BH destination:Source::IndBX displacement:0x3c];
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// sbb %bx,0x16(%bp,%si)
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// xor %sp,0x2c(%si)
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// out %ax,$0xc6
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// jge 0xffffffe0
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[self assert:instructions[18] operation:Operation::SBB size:2 source:Source::BX destination:Source::IndBPPlusSI displacement:0x16];
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[self assert:instructions[19] operation:Operation::XOR size:2 source:Source::SP destination:Source::IndSI displacement:0x2c];
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[self assert:instructions[20] operation:Operation::OUT size:2 source:Source::AX destination:Source::DirectAddress operand:0xc6];
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[self assert:instructions[21] operation:Operation::JNL displacement:0xffb0];
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// mov $0x49,%ch
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// addr32 popa
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// [[ omitted: addr32 popa ]]
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// mov $0xcbc0,%dx
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// adc $0x7e,%al
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// jno 0x0000000b
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[self assert:instructions[22] operation:Operation::MOV size:1 operand:0x49 destination:Source::CH];
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[self assert:instructions[23] operation:Operation::MOV size:2 operand:0xcbc0 destination:Source::DX];
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[self assert:instructions[24] operation:Operation::ADC size:1 operand:0x7e destination:Source::AL];
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[self assert:instructions[25] operation:Operation::JNO displacement:0xffd0];
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// push %ax
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// js 0x0000007b
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// add (%di),%bx
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// in $0xc9,%ax
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[self assert:instructions[26] operation:Operation::PUSH size:2 source:Source::AX];
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[self assert:instructions[27] operation:Operation::JS displacement:0x3d];
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[self assert:instructions[28] operation:Operation::ADD size:2 source:Source::IndDI destination:Source::BX];
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[self assert:instructions[29] operation:Operation::IN size:2 source:Source::DirectAddress destination:Source::AX operand:0xc9];
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// xchg %ax,%di
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// ret
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// fwait
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// out %al,$0xd3
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// insb (%dx),%es:(%di)
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[self assert:instructions[30] operation:Operation::XCHG size:2 source:Source::AX destination:Source::DI];
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[self assert:instructions[31] operation:Operation::RETN];
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[self assert:instructions[32] operation:Operation::WAIT];
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[self assert:instructions[33] operation:Operation::OUT size:1 source:Source::AL destination:Source::DirectAddress operand:0xd3];
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// [[ omitted: insb (%dx),%es:(%di) ]]
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// pop %ax
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// dec %bp
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// jbe 0xffffffcc
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// inc %sp
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[self assert:instructions[34] operation:Operation::POP size:2 destination:Source::AX];
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[self assert:instructions[35] operation:Operation::DEC size:2 source:Source::BP destination:Source::BP];
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[self assert:instructions[36] operation:Operation::JBE displacement:0xff80];
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[self assert:instructions[37] operation:Operation::INC size:2 source:Source::SP destination:Source::SP];
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// (bad)
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// lahf
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// movsw %ds:(%si),%es:(%di)
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// mov $0x12a1,%bp
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[self assert:instructions[38] operation:Operation::Invalid];
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[self assert:instructions[39] operation:Operation::LAHF];
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[self assert:instructions[40] operation:Operation::MOVS size:2];
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[self assert:instructions[41] operation:Operation::MOV size:2 operand:0x12a1 destination:Source::BP];
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// lds (%bx,%di),%bp
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// leave
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// [[ omitted: leave ]]
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// sahf
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// fdiv %st(3),%st
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// iret
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[self assert:instructions[42] operation:Operation::LDS size:4];
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[self assert:instructions[43] operation:Operation::SAHF];
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[self assert:instructions[44] operation:Operation::ESC];
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[self assert:instructions[45] operation:Operation::IRET];
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// xchg %ax,%dx
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// cmp %bx,-0x70(%di)
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// adc $0xb8c3,%ax
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// lods %ds:(%si),%ax
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[self assert:instructions[46] operation:Operation::XCHG size:2 source:Source::AX destination:Source::DX];
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[self assert:instructions[47] operation:Operation::CMP size:2 source:Source::BX destination:Source::IndDI displacement:0xff90];
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[self assert:instructions[48] operation:Operation::ADC size:2 operand:0xb8c3 destination:Source::AX];
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[self assert:instructions[49] operation:Operation::LODS size:2];
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// call 0x0000172d
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// dec %dx
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// mov $0x9e,%al
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// stc
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[self assert:instructions[50] operation:Operation::CALLD operand:0x16c8];
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[self assert:instructions[51] operation:Operation::DEC size:2 source:Source::DX destination:Source::DX];
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[self assert:instructions[52] operation:Operation::MOV size:1 operand:0x9e destination:Source::AL];
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[self assert:instructions[53] operation:Operation::STC];
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// mov $0xea56,%di
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// dec %si
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// std
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// in $0x5a,%al
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[self assert:instructions[54] operation:Operation::MOV size:2 operand:0xea56 destination:Source::DI];
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[self assert:instructions[55] operation:Operation::DEC size:2 source:Source::SI destination:Source::SI];
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[self assert:instructions[56] operation:Operation::STD];
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[self assert:instructions[57] operation:Operation::IN size:1 source:Source::DirectAddress destination:Source::AL operand:0x5a];
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// and 0x5b2c(%bp,%si),%bp
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// sub %dl,%dl
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// negw 0x18(%bx)
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// xchg %dl,0x6425(%bx,%si)
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[self assert:instructions[58] operation:Operation::AND size:2 source:Source::IndBPPlusSI destination:Source::BP displacement:0x5b2c];
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[self assert:instructions[59] operation:Operation::SUB size:1 source:Source::DL destination:Source::DL];
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[self assert:instructions[60] operation:Operation::NEG size:2 source:Source::IndBX destination:Source::IndBX displacement:0x18];
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[self assert:instructions[61] operation:Operation::XCHG size:1 source:Source::IndBXPlusSI destination:Source::DL displacement:0x6425];
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// mov $0xc3,%bh
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[self assert:instructions[62] operation:Operation::MOV size:1 operand:0xc3 destination:Source::BH];
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}
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@end
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@ -51,6 +51,7 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
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#define AddrReg(op, source, op_size, addr_size) \
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SetOpSrcDestSize(op, source, DirectAddress, op_size); \
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operand_size_ = addr_size; \
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destination_ = Source::DirectAddress; \
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phase_ = Phase::AwaitingDisplacementOrOperand
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/// Covers both `mem/reg, reg` and `reg, mem/reg`.
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@ -377,6 +378,13 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
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// Other operand is just a register.
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case 3:
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memreg = reg_table[operation_size_][rm];
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// LES and LDS accept a real memory argument only.
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if(operation_ == Operation::LES || operation_ == Operation::LDS) {
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const auto result = std::make_pair(consumed_, Instruction());
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reset_parsing();
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return result;
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}
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break;
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}
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@ -586,7 +594,6 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
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operand_)
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);
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reset_parsing();
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phase_ = Phase::Instruction;
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return result;
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}
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@ -289,9 +289,11 @@ struct Decoder {
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void reset_parsing() {
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consumed_ = operand_bytes_ = 0;
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displacement_size_ = operand_size_ = 0;
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displacement_ = operand_ = 0;
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lock_ = false;
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segment_override_ = Source::None;
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repetition_ = Repetition::None;
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phase_ = Phase::Instruction;
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}
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};
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