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Merge pull request #629 from TomHarte/MinorSpeedImprovements
Attempts to improve 68000 (and Macintosh) emulation speed
This commit is contained in:
Thomas Harte
GitHub
commit
50e954223a
@ -64,6 +64,7 @@ std::uint8_t z8530::read(int address) {
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}
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pointer_ = 0;
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update_delegate();
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return result;
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}
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@ -110,10 +111,12 @@ void z8530::write(int address, std::uint8_t value) {
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}
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}
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}
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update_delegate();
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}
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void z8530::set_dcd(int port, bool level) {
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channels_[port].set_dcd(level);
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update_delegate();
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}
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// MARK: - Channel implementations
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@ -255,3 +258,11 @@ bool z8530::Channel::get_interrupt_line() {
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(interrupt_mask_ & 1) && external_status_interrupt_;
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// TODO: other potential causes of an interrupt.
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}
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void z8530::update_delegate() {
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const bool interrupt_line = get_interrupt_line();
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if(interrupt_line != previous_interrupt_line_) {
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previous_interrupt_line_ = interrupt_line;
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if(delegate_) delegate_->did_change_interrupt_status(this, interrupt_line);
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}
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}
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@ -35,6 +35,13 @@ class z8530 {
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void reset();
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bool get_interrupt_line();
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struct Delegate {
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virtual void did_change_interrupt_status(z8530 *, bool new_status) = 0;
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};
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void set_delegate(Delegate *delegate) {
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delegate_ = delegate;
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}
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/*
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**Interface for serial port input.**
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*/
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@ -79,6 +86,10 @@ class z8530 {
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uint8_t interrupt_vector_ = 0;
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uint8_t master_interrupt_control_ = 0;
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bool previous_interrupt_line_ = false;
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void update_delegate();
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Delegate *delegate_ = nullptr;
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};
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}
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@ -51,7 +51,8 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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public MediaTarget::Machine,
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public MouseMachine::Machine,
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public CPU::MC68000::BusHandler,
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public KeyboardMachine::MappedMachine {
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public KeyboardMachine::MappedMachine,
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public Zilog::SCC::z8530::Delegate {
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public:
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using Target = Analyser::Static::Macintosh::Target;
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@ -112,6 +113,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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iwm_.iwm.set_drive(0, &drives_[0]);
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iwm_.iwm.set_drive(1, &drives_[1]);
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// Make sure interrupt changes from the SCC are observed.
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scc_.set_delegate(this);
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// The Mac runs at 7.8336mHz.
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set_clock_rate(double(CLOCK_RATE));
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audio_.speaker.set_input_rate(float(CLOCK_RATE) / 2.0f);
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@ -208,16 +212,6 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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via_.set_control_line_input(MOS::MOS6522::Port::A, MOS::MOS6522::Line::Two, false);
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}
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// Update interrupt input. TODO: move this into a VIA/etc delegate callback?
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// Double TODO: does this really cascade like this?
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if(scc_.get_interrupt_line()) {
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mc68000_.set_interrupt_level(2);
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} else if(via_.get_interrupt_line()) {
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mc68000_.set_interrupt_level(1);
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} else {
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mc68000_.set_interrupt_level(0);
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}
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// A null cycle leaves nothing else to do.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return delay;
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@ -319,7 +313,14 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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) {
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memory_base = ram_;
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word_address &= ram_mask_;
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update_video();
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// This is coupled with the Macintosh implementation of video; the magic
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// constant should probably be factored into the Video class.
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// It embodies knowledge of the fact that video (and audio) will always
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// be fetched from the final $d900 bytes (i.e. $6c80 words) of memory.
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// (And that ram_mask_ = ram size - 1).
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// if(word_address > ram_mask_ - 0x6c80)
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update_video();
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} else {
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memory_base = rom_;
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word_address &= rom_mask_;
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@ -433,6 +434,24 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// TODO: clear all keys.
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// MARK: Interrupt updates.
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void did_change_interrupt_status(Zilog::SCC::z8530 *sender, bool new_status) override {
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update_interrupt_input();
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}
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void update_interrupt_input() {
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// Update interrupt input.
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// TODO: does this really cascade like this?
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if(scc_.get_interrupt_line()) {
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mc68000_.set_interrupt_level(2);
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} else if(via_.get_interrupt_line()) {
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mc68000_.set_interrupt_level(1);
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} else {
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mc68000_.set_interrupt_level(0);
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}
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}
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private:
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void update_video() {
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video_.run_for(time_since_video_update_.flush());
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@ -554,6 +573,10 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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audio_.flush();
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}
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void set_interrupt_status(bool status) {
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machine_.update_interrupt_input();
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}
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private:
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ConcreteMachine &machine_;
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RealTimeClock &clock_;
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@ -49,7 +49,7 @@ class CPU::MC68000::ProcessorStorageTests {
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if(!strcmp(type, "VA")) {
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// Test for validity.
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if(!storage.instructions[next_opcode].micro_operations) {
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if(storage.instructions[next_opcode].micro_operations == std::numeric_limits<uint32_t>::max()) {
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[false_invalids_ addObject:@(next_opcode)];
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}
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continue;
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@ -57,7 +57,7 @@ class CPU::MC68000::ProcessorStorageTests {
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if(!strcmp(type, "IN")) {
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// Test for invalidity.
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if(storage.instructions[next_opcode].micro_operations) {
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if(storage.instructions[next_opcode].micro_operations != std::numeric_limits<uint32_t>::max()) {
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[false_valids_ addObject:@(next_opcode)];
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}
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continue;
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@ -104,7 +104,8 @@ class EmuTOS: public ComparativeBusHandler {
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}
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- (void)testImage:(NSString *)image trace:(NSString *)trace length:(int)length {
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const auto roms = CSROMFetcher()("AtariST", { image.UTF8String });
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const std::vector<ROMMachine::ROM> rom_names = {{"AtariST", "", image.UTF8String, 0, 0 }};
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const auto roms = CSROMFetcher()(rom_names);
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NSString *const traceLocation = [[NSBundle bundleForClass:[self class]] pathForResource:trace ofType:@"trace.txt.gz"];
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_machine.reset(new EmuTOS(*roms[0], traceLocation.UTF8String));
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_machine->run_for(HalfCycles(length));
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@ -101,7 +101,8 @@ class QL: public ComparativeBusHandler {
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Tests the progression of Clock Signal's 68000 through the Sinclair QL's ROM against a known-good trace.
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*/
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- (void)testStartup {
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const auto roms = CSROMFetcher()("SinclairQL", {"js.rom"});
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const std::vector<ROMMachine::ROM> rom_names = {{"SinclairQL", "", "js.rom", 0, 0 }};
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const auto roms = CSROMFetcher()(rom_names);
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NSString *const traceLocation = [[NSBundle bundleForClass:[self class]] pathForResource:@"qltrace" ofType:@".txt.gz"];
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_machine.reset(new QL(*roms[0], traceLocation.UTF8String));
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@ -9,10 +9,12 @@
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#ifndef MC68000_h
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#define MC68000_h
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#include <cassert>
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#include <cstdint>
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#include <cstring>
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#include <iomanip>
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#include <iostream>
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#include <limits>
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#include <ostream>
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#include <vector>
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File diff suppressed because it is too large
Load Diff
@ -473,7 +473,7 @@ struct ProcessorStorageConstructor {
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void replace_write_values(ProcessorBase::MicroOp *start, const std::initializer_list<RegisterPair16 *> &values) {
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auto value = values.begin();
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while(!start->is_terminal()) {
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value = replace_write_values(start->bus_program, value);
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value = replace_write_values(&storage_.all_bus_steps_[start->bus_program], value);
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++start;
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}
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assert(value == values.end());
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@ -827,10 +827,10 @@ struct ProcessorStorageConstructor {
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// The arbitrary_base is used so that the offsets returned by assemble_program into
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// storage_.all_bus_steps_ can be retained and mapped into the final version of
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// storage_.all_bus_steps_ at the end.
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BusStep arbitrary_base;
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// BusStep arbitrary_base;
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#define op(...) storage_.all_micro_ops_.emplace_back(__VA_ARGS__)
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#define seq(...) &arbitrary_base + assemble_program(__VA_ARGS__)
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#define seq(...) assemble_program(__VA_ARGS__)
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#define ea(n) &storage_.effective_address_[n].full
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#define a(n) &storage_.address_[n].full
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@ -862,16 +862,12 @@ struct ProcessorStorageConstructor {
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// Temporary storage for the Program fields.
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ProcessorBase::Program program;
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// if(instruction == 0x4879) {
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// printf("");
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// }
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#define dec(n) decrement_action(is_long_word_access, is_byte_access, n)
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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switch(mapping.decoder) {
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case Decoder::STOP: {
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program.requires_supervisor = true;
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program.set_requires_supervisor(true);
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op(Action::None, seq("n"));
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op(Action::PerformOperation);
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} break;
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@ -977,7 +973,7 @@ struct ProcessorStorageConstructor {
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case Decoder::EORI_ORI_ANDI_SR: {
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// The source used here is always the high word of the prefetch queue.
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program.requires_supervisor = !!(instruction & 0x40);
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program.set_requires_supervisor(!!(instruction & 0x40));
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op(Action::None, seq("np nn nn"));
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op(Action::PerformOperation, seq("np np"));
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} break;
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@ -1015,7 +1011,7 @@ struct ProcessorStorageConstructor {
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} break;
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case Decoder::RTE_RTR: {
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program.requires_supervisor = instruction == 0x4e73;
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program.set_requires_supervisor(instruction == 0x4e73);
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// TODO: something explicit to ensure the nR nr nr is exclusively linked.
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op(Action::PrepareRTE_RTR, seq("nR nr nr", { &storage_.precomputed_addresses_[0], &storage_.precomputed_addresses_[1], &storage_.precomputed_addresses_[2] } ));
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@ -1269,13 +1265,8 @@ struct ProcessorStorageConstructor {
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// Source is always something cribbed from the instruction stream;
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// destination is going to be in the write address unit.
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program.source = &storage_.source_bus_data_[0];
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if(mode == Dn) {
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program.destination = &storage_.data_[ea_register];
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} else {
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program.destination = &storage_.destination_bus_data_[0];
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program.destination_address = &storage_.address_[ea_register];
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}
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program.set_source(storage_, Imm, 0);
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program.set_destination(storage_, mode, ea_register);
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switch(is_long_word_access ? l(mode) : bw(mode)) {
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default: continue;
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@ -1371,33 +1362,36 @@ struct ProcessorStorageConstructor {
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const int mode = combined_mode(ea_mode, ea_register);
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if(reverse_source_destination) {
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program.destination = &storage_.data_[data_register];
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program.source = &storage_.source_bus_data_[0];
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program.source_address = &storage_.address_[ea_register];
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program.set_destination(storage_, Dn, data_register);
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program.set_source(storage_, Imm, ea_register);
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// Perform [ADD/SUB].blw <ea>, Dn
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switch(is_long_word_access ? l(mode) : bw(mode)) {
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default: continue;
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case bw(Dn): // ADD/SUB.bw Dn, Dn
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program.source = &storage_.data_[ea_register];
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program.set_source(storage_, Dn, ea_register);
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// program.source = &storage_.data_[ea_register];
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op(Action::PerformOperation, seq("np"));
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break;
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case l(Dn): // ADD/SUB.l Dn, Dn
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program.source = &storage_.data_[ea_register];
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program.set_source(storage_, Dn, ea_register);
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// program.source = &storage_.data_[ea_register];
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op(Action::PerformOperation, seq("np nn"));
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break;
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case bw(An): // ADD/SUB.bw An, Dn
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// Address registers can't provide single bytes.
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if(is_byte_access) continue;
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program.source = &storage_.address_[ea_register];
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program.set_source(storage_, An, ea_register);
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// program.source = &storage_.address_[ea_register];
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op(Action::PerformOperation, seq("np"));
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break;
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case l(An): // ADD/SUB.l An, Dn
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program.source = &storage_.address_[ea_register];
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program.set_source(storage_, An, ea_register);
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// program.source = &storage_.address_[ea_register];
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op(Action::PerformOperation, seq("np nn"));
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break;
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@ -1469,11 +1463,9 @@ struct ProcessorStorageConstructor {
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break;
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}
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} else {
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program.source = &storage_.data_[data_register];
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const auto destination_register = ea_register;
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program.destination = &storage_.destination_bus_data_[0];
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program.destination_address = &storage_.address_[destination_register];
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program.set_destination(storage_, Ind, destination_register);
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program.set_source(storage_, Dn, data_register);
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// Perform [ADD/SUB].blw Dn, <ea>
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switch(is_long_word_access ? l(mode) : bw(mode)) {
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@ -1782,7 +1774,7 @@ struct ProcessorStorageConstructor {
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case Ind: // BTST.b Dn, (An)
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case PostInc: // BTST.b Dn, (An)+
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op(Action::None, seq("nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
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if(mode == PostInc) {
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op(byte_inc(ea_register) | MicroOp::DestinationMask);
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}
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@ -1790,7 +1782,7 @@ struct ProcessorStorageConstructor {
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case PreDec: // BTST.b Dn, -(An)
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op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
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break;
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case XXXl: // BTST.b Dn, (xxx).l
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@ -1805,7 +1797,7 @@ struct ProcessorStorageConstructor {
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op( address_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nrd np", mode), { ea(1) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
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break;
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case Imm: // BTST.b Dn, #
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@ -1822,7 +1814,7 @@ struct ProcessorStorageConstructor {
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case Decoder::BTSTIMM: {
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const bool is_bclr = mapping.decoder == Decoder::BCLRIMM;
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program.source = &storage_.source_bus_data_[0];
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program.set_source(storage_, Imm, 0);
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program.set_destination(storage_, ea_mode, ea_register);
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const int mode = combined_mode(ea_mode, ea_register);
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@ -1844,7 +1836,7 @@ struct ProcessorStorageConstructor {
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case Ind: // BTST.b #, (An)
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case PostInc: // BTST.b #, (An)+
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
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if(mode == PostInc) {
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op(byte_inc(ea_register) | MicroOp::DestinationMask);
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}
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@ -1853,7 +1845,7 @@ struct ProcessorStorageConstructor {
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case PreDec: // BTST.b #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
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break;
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case XXXw: // BTST.b #, (xxx).w
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@ -1867,14 +1859,14 @@ struct ProcessorStorageConstructor {
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( address_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nrd np", mode), { ea(1) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
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op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
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break;
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case XXXl: // BTST.b #, (xxx).l
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op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
|
||||
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
|
||||
break;
|
||||
}
|
||||
} break;
|
||||
@ -2013,7 +2005,7 @@ struct ProcessorStorageConstructor {
|
||||
} break;
|
||||
|
||||
case Decoder::CMP: {
|
||||
program.destination = &storage_.data_[data_register];
|
||||
program.set_destination(storage_, Dn, data_register);
|
||||
program.set_source(storage_, ea_mode, ea_register);
|
||||
|
||||
// Byte accesses are not allowed with address registers.
|
||||
@ -2090,12 +2082,12 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case bw(Imm): // CMP.br #, Dn
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::PerformOperation, seq("np np"));
|
||||
break;
|
||||
|
||||
case l(Imm): // CMP.l #, Dn
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::None, seq("np"));
|
||||
op(Action::PerformOperation, seq("np np n"));
|
||||
break;
|
||||
@ -2109,7 +2101,7 @@ struct ProcessorStorageConstructor {
|
||||
is_long_word_access = op_mode == 7;
|
||||
|
||||
program.set_source(storage_, ea_mode, ea_register);
|
||||
program.destination = &storage_.address_[data_register];
|
||||
program.set_destination(storage_, An, data_register);
|
||||
|
||||
const int mode = combined_mode(ea_mode, ea_register, true);
|
||||
switch(is_long_word_access ? l(mode) : bw(mode)) {
|
||||
@ -2172,12 +2164,12 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case bw(Imm): // CMPA.w #, An
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::PerformOperation, seq("np np n"));
|
||||
break;
|
||||
|
||||
case l(Imm): // CMPA.l #, An
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::None, seq("np"));
|
||||
op(Action::PerformOperation, seq("np np n"));
|
||||
break;
|
||||
@ -2190,7 +2182,7 @@ struct ProcessorStorageConstructor {
|
||||
const auto destination_mode = ea_mode;
|
||||
const auto destination_register = ea_register;
|
||||
|
||||
program.source = &storage_.source_bus_data_[0];
|
||||
program.set_source(storage_, Imm, 0); // i.e. from the fetched data latch.
|
||||
program.set_destination(storage_, destination_mode, destination_register);
|
||||
|
||||
const int mode = combined_mode(destination_mode, destination_register);
|
||||
@ -2198,12 +2190,12 @@ struct ProcessorStorageConstructor {
|
||||
default: continue;
|
||||
|
||||
case bw(Dn): // CMPI.bw #, Dn
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::PerformOperation, seq("np np"));
|
||||
break;
|
||||
|
||||
case l(Dn): // CMPI.l #, Dn
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(Action::None, seq("np"));
|
||||
op(Action::PerformOperation, seq("np np n"));
|
||||
break;
|
||||
@ -2314,7 +2306,7 @@ struct ProcessorStorageConstructor {
|
||||
if(ea_mode == 1) {
|
||||
// This is a DBcc. Decode as such.
|
||||
operation = Operation::DBcc;
|
||||
program.source = &storage_.data_[ea_register];
|
||||
program.set_source(storage_, Dn, ea_register);
|
||||
|
||||
// Jump straight into deciding what steps to take next,
|
||||
// which will be selected dynamically.
|
||||
@ -2371,7 +2363,7 @@ struct ProcessorStorageConstructor {
|
||||
program.set_source(storage_, ea_mode, ea_register);
|
||||
|
||||
// ... but otherwise assume that the true source of a destination will be the computed source address.
|
||||
program.source = &storage_.effective_address_[0];
|
||||
program.set_source(storage_, &storage_.effective_address_[0]);
|
||||
|
||||
const int mode = combined_mode(ea_mode, ea_register);
|
||||
switch(mode) {
|
||||
@ -2445,8 +2437,7 @@ struct ProcessorStorageConstructor {
|
||||
|
||||
case Decoder::PEA: {
|
||||
program.set_source(storage_, An, ea_register);
|
||||
program.destination = &storage_.destination_bus_data_[0];
|
||||
program.destination_address = &storage_.address_[7];
|
||||
program.set_destination(storage_, Imm, 7); // Immediate destination => store to the destination bus latch.
|
||||
|
||||
const int mode = combined_mode(ea_mode, ea_register);
|
||||
switch(mode) {
|
||||
@ -2461,7 +2452,7 @@ struct ProcessorStorageConstructor {
|
||||
|
||||
case XXXl: // PEA (XXX).l
|
||||
case XXXw: // PEA (XXX).w
|
||||
op(int(Action::Decrement4) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
|
||||
op(int(Action::Decrement4) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : MicroOp::NoBusProgram);
|
||||
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
|
||||
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
|
||||
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
@ -2483,11 +2474,11 @@ struct ProcessorStorageConstructor {
|
||||
program.set_destination(storage_, An, data_register);
|
||||
|
||||
const int mode = combined_mode(ea_mode, ea_register);
|
||||
program.source_address = &storage_.address_[ea_register];
|
||||
program.source =
|
||||
program.set_source_address(storage_, ea_register);
|
||||
program.set_source(storage_,
|
||||
(mode == Ind) ?
|
||||
&storage_.address_[ea_register] :
|
||||
&storage_.effective_address_[0];
|
||||
&storage_.effective_address_[0]);
|
||||
|
||||
switch(mode) {
|
||||
default: continue;
|
||||
@ -2553,7 +2544,7 @@ struct ProcessorStorageConstructor {
|
||||
case Decoder::MOVEtoSRCCR: {
|
||||
if(ea_mode == An) continue;
|
||||
program.set_source(storage_, ea_mode, ea_register);
|
||||
program.requires_supervisor = (operation == Operation::MOVEtoSR);
|
||||
program.set_requires_supervisor(operation == Operation::MOVEtoSR);
|
||||
|
||||
/* DEVIATION FROM YACHT.TXT: it has all of these reading an extra word from the PC;
|
||||
this looks like a mistake so I've padded with nil cycles in the middle. */
|
||||
@ -2591,14 +2582,14 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case Imm: // MOVE #, SR
|
||||
program.source = &storage_.prefetch_queue_;
|
||||
program.set_source(storage_, &storage_.prefetch_queue_);
|
||||
op(int(Action::PerformOperation), seq("np nn nn np"));
|
||||
break;
|
||||
}
|
||||
} break;
|
||||
|
||||
case Decoder::MOVEq: {
|
||||
program.destination = &storage_.data_[data_register];
|
||||
program.set_destination(storage_, Dn, data_register);
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
} break;
|
||||
|
||||
@ -2679,18 +2670,18 @@ struct ProcessorStorageConstructor {
|
||||
} break;
|
||||
|
||||
case Decoder::MOVEUSP: {
|
||||
program.requires_supervisor = true;
|
||||
program.set_requires_supervisor(true);
|
||||
|
||||
// Observation here: because this is a privileged instruction, the user stack pointer
|
||||
// definitely isn't currently [copied into] A7.
|
||||
if(instruction & 0x8) {
|
||||
// Transfer FROM the USP.
|
||||
program.source = &storage_.stack_pointers_[0];
|
||||
program.set_source(storage_, &storage_.stack_pointers_[0]);
|
||||
program.set_destination(storage_, An, ea_register);
|
||||
} else {
|
||||
// Transfer TO the USP.
|
||||
program.set_source(storage_, An, ea_register);
|
||||
program.destination = &storage_.stack_pointers_[0];
|
||||
program.set_destination(storage_, &storage_.stack_pointers_[0]);
|
||||
}
|
||||
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
@ -2878,7 +2869,7 @@ struct ProcessorStorageConstructor {
|
||||
} break;
|
||||
|
||||
case Decoder::RESET:
|
||||
program.requires_supervisor = true;
|
||||
program.set_requires_supervisor(true);
|
||||
op(Action::None, seq("nn _ np"));
|
||||
break;
|
||||
|
||||
@ -3088,28 +3079,29 @@ struct ProcessorStorageConstructor {
|
||||
Iterates through the micro-sequence beginning at @c start, finalising bus_program
|
||||
pointers that have been transiently stored as relative to @c arbitrary_base.
|
||||
*/
|
||||
const auto link_operations = [this](MicroOp *start, BusStep *arbitrary_base) {
|
||||
while(!start->is_terminal()) {
|
||||
const auto offset = size_t(start->bus_program - arbitrary_base);
|
||||
assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
|
||||
start->bus_program = &storage_.all_bus_steps_[offset];
|
||||
++start;
|
||||
}
|
||||
};
|
||||
// const auto link_operations = [this](MicroOp *start, BusStep *arbitrary_base) {
|
||||
// while(!start->is_terminal()) {
|
||||
// const auto offset = size_t(start->bus_program - arbitrary_base);
|
||||
// assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
|
||||
// start->bus_program = &storage_.all_bus_steps_[offset];
|
||||
// ++start;
|
||||
// }
|
||||
// };
|
||||
|
||||
// Finalise micro-op and program pointers.
|
||||
for(size_t instruction = 0; instruction < 65536; ++instruction) {
|
||||
if(micro_op_pointers[instruction] != std::numeric_limits<size_t>::max()) {
|
||||
storage_.instructions[instruction].micro_operations = &storage_.all_micro_ops_[micro_op_pointers[instruction]];
|
||||
link_operations(storage_.instructions[instruction].micro_operations, &arbitrary_base);
|
||||
storage_.instructions[instruction].micro_operations = uint32_t(micro_op_pointers[instruction]);
|
||||
// link_operations(&storage_.all_micro_ops_[micro_op_pointers[instruction]], &arbitrary_base);
|
||||
}
|
||||
}
|
||||
|
||||
// Link up the interrupt micro ops.
|
||||
storage_.interrupt_micro_ops_ = &storage_.all_micro_ops_[interrupt_pointer];
|
||||
link_operations(storage_.interrupt_micro_ops_, &arbitrary_base);
|
||||
// link_operations(storage_.interrupt_micro_ops_, &arbitrary_base);
|
||||
|
||||
std::cout << storage_.all_bus_steps_.size() << " total steps" << std::endl;
|
||||
std::cout << storage_.all_bus_steps_.size() << " total bus steps" << std::endl;
|
||||
std::cout << storage_.all_micro_ops_.size() << " total micro ops" << std::endl;
|
||||
}
|
||||
|
||||
private:
|
||||
@ -3257,7 +3249,7 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
|
||||
//
|
||||
// Assumed order of input: PC.h, SR, PC.l (i.e. the opposite of TRAP's output).
|
||||
for(const int instruction: { 0x4e73, 0x4e77 }) {
|
||||
auto steps = instructions[instruction].micro_operations[0].bus_program;
|
||||
auto steps = &all_bus_steps_[all_micro_ops_[instructions[instruction].micro_operations].bus_program];
|
||||
steps[0].microcycle.value = steps[1].microcycle.value = &program_counter_.halves.high;
|
||||
steps[4].microcycle.value = steps[5].microcycle.value = &program_counter_.halves.low;
|
||||
}
|
||||
@ -3267,10 +3259,10 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
|
||||
|
||||
// Complete linkage of the exception micro program.
|
||||
short_exception_micro_ops_ = &all_micro_ops_[short_exception_offset];
|
||||
short_exception_micro_ops_->bus_program = trap_steps_;
|
||||
short_exception_micro_ops_->bus_program = trap_offset;
|
||||
|
||||
long_exception_micro_ops_ = &all_micro_ops_[long_exception_offset];
|
||||
long_exception_micro_ops_->bus_program = bus_error_steps_;
|
||||
long_exception_micro_ops_->bus_program = bus_error_offset;
|
||||
|
||||
// Set initial state.
|
||||
active_step_ = reset_bus_steps_;
|
||||
|
||||
@ -74,7 +74,7 @@ class ProcessorStorage {
|
||||
HalfCycles half_cycles_left_to_run_;
|
||||
HalfCycles e_clock_phase_;
|
||||
|
||||
enum class Operation {
|
||||
enum class Operation: uint8_t {
|
||||
None,
|
||||
ABCD, SBCD, NBCD,
|
||||
|
||||
@ -216,7 +216,7 @@ class ProcessorStorage {
|
||||
be performed.
|
||||
*/
|
||||
struct MicroOp {
|
||||
enum class Action: int {
|
||||
enum class Action: uint8_t {
|
||||
None,
|
||||
|
||||
/// Does whatever this instruction says is the main operation.
|
||||
@ -312,21 +312,22 @@ class ProcessorStorage {
|
||||
// steps detail appropriately.
|
||||
PrepareINTVector,
|
||||
};
|
||||
static const int SourceMask = 1 << 30;
|
||||
static const int DestinationMask = 1 << 29;
|
||||
int action = int(Action::None);
|
||||
static const int SourceMask = 1 << 7;
|
||||
static const int DestinationMask = 1 << 6;
|
||||
uint8_t action = uint8_t(Action::None);
|
||||
|
||||
BusStep *bus_program = nullptr;
|
||||
static const uint16_t NoBusProgram = std::numeric_limits<uint16_t>::max();
|
||||
uint16_t bus_program = NoBusProgram;
|
||||
|
||||
MicroOp() {}
|
||||
MicroOp(int action) : action(action) {}
|
||||
MicroOp(int action, BusStep *bus_program) : action(action), bus_program(bus_program) {}
|
||||
MicroOp(uint8_t action) : action(action) {}
|
||||
MicroOp(uint8_t action, uint16_t bus_program) : action(action), bus_program(bus_program) {}
|
||||
|
||||
MicroOp(Action action) : MicroOp(int(action)) {}
|
||||
MicroOp(Action action, BusStep *bus_program) : MicroOp(int(action), bus_program) {}
|
||||
MicroOp(Action action) : MicroOp(uint8_t(action)) {}
|
||||
MicroOp(Action action, uint16_t bus_program) : MicroOp(uint8_t(action), bus_program) {}
|
||||
|
||||
forceinline bool is_terminal() const {
|
||||
return bus_program == nullptr;
|
||||
return bus_program == std::numeric_limits<uint16_t>::max();
|
||||
}
|
||||
};
|
||||
|
||||
@ -334,31 +335,70 @@ class ProcessorStorage {
|
||||
A program represents the implementation of a particular opcode, as a sequence
|
||||
of micro-ops and, separately, the operation to perform plus whatever other
|
||||
fields the operation requires.
|
||||
|
||||
Some of the fields are slightly convoluted in how they identify the information
|
||||
they reference; this is done to keep this struct as small as possible due to
|
||||
concerns about cache size.
|
||||
|
||||
On the 64-bit Intel processor this emulator was developed on, the struct below
|
||||
adds up to 8 bytes; four for the initial uint32_t and then one each for the
|
||||
remaining fields, with no additional padding being inserted by the compiler.
|
||||
*/
|
||||
struct Program {
|
||||
MicroOp *micro_operations = nullptr;
|
||||
RegisterPair32 *source = nullptr;
|
||||
RegisterPair32 *destination = nullptr;
|
||||
RegisterPair32 *source_address = nullptr;
|
||||
RegisterPair32 *destination_address = nullptr;
|
||||
/// The offset into the all_micro_ops_ at which micro-ops for this instruction begin,
|
||||
/// or std::numeric_limits<uint32_t>::max() if this is an invalid Program.
|
||||
uint32_t micro_operations = std::numeric_limits<uint32_t>::max();
|
||||
/// The overarching operation applied by this program when the moment comes.
|
||||
Operation operation;
|
||||
bool requires_supervisor = false;
|
||||
/// The number of bytes after the beginning of an instance of ProcessorStorage that the RegisterPair32 containing
|
||||
/// a source value for this operation lies at.
|
||||
uint8_t source_offset = 0;
|
||||
/// The number of bytes after the beginning of an instance of ProcessorStorage that the RegisterPair32 containing
|
||||
/// a destination value for this operation lies at.
|
||||
uint8_t destination_offset = 0;
|
||||
/// A bitfield comprised of:
|
||||
/// b7 = set if this program requires supervisor mode;
|
||||
/// b0–b2 = the source address register (for pre-decrement and post-increment actions); and
|
||||
/// b4-b6 = destination address register.
|
||||
uint8_t source_dest = 0;
|
||||
|
||||
void set_source_address(ProcessorStorage &storage, int index) {
|
||||
source_dest = uint8_t((source_dest & 0x0f) | (index << 4));
|
||||
}
|
||||
|
||||
void set_destination_address(ProcessorStorage &storage, int index) {
|
||||
source_dest = uint8_t((source_dest & 0xf0) | index);
|
||||
}
|
||||
|
||||
void set_requires_supervisor(bool requires_supervisor) {
|
||||
source_dest = (source_dest & 0x7f) | (requires_supervisor ? 0x80 : 0x00);
|
||||
}
|
||||
|
||||
void set_source(ProcessorStorage &storage, RegisterPair32 *target) {
|
||||
source_offset = decltype(source_offset)(reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage));
|
||||
assert(source_offset == (reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage)));
|
||||
}
|
||||
|
||||
void set_destination(ProcessorStorage &storage, RegisterPair32 *target) {
|
||||
destination_offset = decltype(destination_offset)(reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage));
|
||||
assert(destination_offset == (reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage)));
|
||||
}
|
||||
|
||||
void set_source(ProcessorStorage &storage, int mode, int reg) {
|
||||
source_address = &storage.address_[reg];
|
||||
set_source_address(storage, reg);
|
||||
switch(mode) {
|
||||
case 0: source = &storage.data_[reg]; break;
|
||||
case 1: source = &storage.address_[reg]; break;
|
||||
default: source = &storage.source_bus_data_[0]; break;
|
||||
case 0: set_source(storage, &storage.data_[reg]); break;
|
||||
case 1: set_source(storage, &storage.address_[reg]); break;
|
||||
default: set_source(storage, &storage.source_bus_data_[0]); break;
|
||||
}
|
||||
}
|
||||
|
||||
void set_destination(ProcessorStorage &storage, int mode, int reg) {
|
||||
destination_address = &storage.address_[reg];
|
||||
set_destination_address(storage, reg);
|
||||
switch(mode) {
|
||||
case 0: destination = &storage.data_[reg]; break;
|
||||
case 1: destination = &storage.address_[reg]; break;
|
||||
default: destination = &storage.destination_bus_data_[0]; break;
|
||||
case 0: set_destination(storage, &storage.data_[reg]); break;
|
||||
case 1: set_destination(storage, &storage.address_[reg]); break;
|
||||
default: set_destination(storage, &storage.destination_bus_data_[0]); break;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user