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https://github.com/TomHarte/CLK.git
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Expose full bus to IOC dependents; add notes.
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Thomas Harte
parent
ae684edbe1
commit
521fca6089
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@ -15,6 +15,20 @@
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namespace InstructionSet::ARM {
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/// Maps from a semantic ARM read of type @c SourceT to either the 8- or 32-bit value observed
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/// by watching the low 8 bits or all 32 bits of the data bus.
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template <typename DestinationT, typename SourceT>
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DestinationT read_bus(SourceT value) {
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if constexpr (std::is_same_v<DestinationT, SourceT>) {
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return value;
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}
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if constexpr (std::is_same_v<DestinationT, uint8_t>) {
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return uint8_t(value);
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} else {
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return value | (value << 8) | (value << 16) | (value << 24);
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}
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}
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/// A class compatible with the @c OperationMapper definition of a scheduler which applies all actions
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/// immediately, updating either a set of @c Registers or using the templated @c MemoryT to access
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/// memory. No hooks are currently provided for applying realistic timing.
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@ -142,7 +142,7 @@ class ConcreteMachine:
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return executor_.bus.video().crt().get_scaled_scan_status();
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}
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std::array<uint32_t, 750> pc_history;
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std::array<uint32_t, 75> pc_history;
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std::size_t pc_history_ptr = 0;
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uint32_t instr_count = 0;
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@ -168,7 +168,7 @@ class ConcreteMachine:
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static bool log = false;
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static bool accumulate = false;
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// if(executor_.pc() == 0x03803400) {
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// if(executor_.pc() == 0x03801ed8 || executor_.registers()[9] == 0x00ff'0000) {
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// printf("At %08x; after last PC %08x and %zu ago was %08x\n", executor_.pc(), pc_history[(pc_history_ptr - 2 + pc_history.size()) % pc_history.size()], pc_history.size(), pc_history[pc_history_ptr]);
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// }
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@ -186,7 +186,7 @@ class ConcreteMachine:
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}
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// TODO: pipeline prefetch?
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// log |= executor_.pc() == 0x3961244;
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// log |= executor_.pc() == 0x03801ebc;
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// log |= instr_count == 72766815;
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// log &= executor_.pc() != 0x000000a0;
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@ -128,15 +128,16 @@ struct InputOutputController {
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/// Access type.
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enum class Type {
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Sync = 0b00,
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Fast = 0b01,
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Medium = 0b10,
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Fast = 0b10,
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Medium = 0b01,
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Slow = 0b11
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} type;
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};
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bool read(uint32_t address, uint8_t &value) {
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template <typename IntT>
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bool read(uint32_t address, IntT &value) {
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const Address target(address);
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value = 0xff;
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value = IntT(~0);
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switch(target.bank) {
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default:
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@ -217,13 +218,22 @@ struct InputOutputController {
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// logger.error().append("%02x: Counter %d high is %02x", target, (target >> 4) - 0x4, value);
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break;
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}
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return true;
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break;
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}
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// if constexpr (std::is_same_v<IntT, uint8_t>) {
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// } else {
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// // TODO: generalise this adaptation of an 8-bit device to the 32-bit bus, which probably isn't right anyway.
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// uint8_t value;
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// ioc_.read(address, value);
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// source = value;
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// }
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return true;
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}
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bool write(uint32_t address, uint8_t value) {
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template <typename IntT>
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bool write(uint32_t address, IntT value) {
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const Address target(address);
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switch(target.bank) {
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default:
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@ -238,13 +248,21 @@ struct InputOutputController {
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break;
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case 0x00:
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// TODO: does the rest of the control register relate to anything?
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control_ = value;
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control_ = static_cast<uint8_t>(value);
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i2c_.set_clock_data(!(value & 2), !(value & 1));
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// Per the A500 documentation:
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// b7: vertical sync/test input bit, so should be programmed high;
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// b6: input for printer acknowledgement, so should be programmed high;
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// b5: speaker mute; 1 = muted;
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// b4: "Available on the auxiliary I/O connector"
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// b3: "Programmed HIGH, unless Reset Mask is required."
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// b2: Used as the floppy disk (READY) input and must be programmed high;
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// b1 and b0: I2C connections as above.
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break;
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case 0x04:
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serial_.output(IOCParty, value);
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serial_.output(IOCParty, static_cast<uint8_t>(value));
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irq_b_.clear(IRQB::KeyboardTransmitEmpty);
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observer_.update_interrupts();
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break;
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@ -260,9 +278,9 @@ struct InputOutputController {
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break;
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// Interrupts.
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case 0x18: irq_a_.mask = value; break;
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case 0x28: irq_b_.mask = value; break;
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case 0x38: fiq_.mask = value; break;
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case 0x18: irq_a_.mask = static_cast<uint8_t>(value); break;
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case 0x28: irq_b_.mask = static_cast<uint8_t>(value); break;
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case 0x38: fiq_.mask = static_cast<uint8_t>(value); break;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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@ -285,7 +303,48 @@ struct InputOutputController {
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counters_[(target.offset >> 4) - 0x4].output = counters_[(target.offset >> 4) - 0x4].value;
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break;
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}
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return true;
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break;
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// Bank 5: both the hard disk and the latches, depending on type.
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case 5:
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switch(target.type) {
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default:
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logger.error().append("Unrecognised IOC bank 5 type %d write; %02x to offset %02x", target.type, value, target.offset);
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break;
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case Address::Type::Fast:
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switch(target.offset) {
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default:
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logger.error().append("Unrecognised IOC fast bank 5 write; %02x to offset %02x", value, target.offset);
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break;
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}
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break;
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// TODO, per the A500 documentation:
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//
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// Latch A:
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// b0, b1, b2, b3 = drive selects;
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// b4 = side select;
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// b5 = motor on/off
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// b6 = floppy in use (i.e. LED?);
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// b7 = "Not used."
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//
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// Latch B:
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// b0: ?
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// b1: double/single density; 0 = double.
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// b2: ?
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// b3: floppy drive reset; 0 = reset.
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// b4: printer strobe
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// b5: ?
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// b6: ?
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// b7: HS3?
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//
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// Latch C:
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// (probably not present on earlier machines?)
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// b2/b3: sync polarity [b3 = V polarity, b2 = H?]
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// b0/b1: VIDC master clock; 00 = 24Mhz, 01 = 25.175Mhz; 10 = 36Mhz; 11 = reserved.
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}
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break;
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}
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// case 0x327'0000 & AddressMask: // Bank 7
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@ -114,8 +114,7 @@ struct MemoryController {
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} break;
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case Zone::IOControllers:
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// TODO: have I overrestricted the value type for the IOC area?
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ioc_.write(address, uint8_t(source));
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ioc_.template write<IntT>(address, source);
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break;
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case Zone::VideoController:
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@ -172,16 +171,9 @@ struct MemoryController {
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source = high_rom<IntT>(address);
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break;
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case Zone::IOControllers: {
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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ioc_.read(address, source);
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} else {
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// TODO: generalise this adaptation of an 8-bit device to the 32-bit bus, which probably isn't right anyway.
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uint8_t value;
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ioc_.read(address, value);
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source = value;
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}
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} break;
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case Zone::IOControllers:
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ioc_.template read<IntT>(address, source);
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break;
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default:
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logger.error().append("TODO: read from %08x", address);
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