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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-10 12:29:01 +00:00

It looks like writes should always go to RAM.

Now I see the screen buffer being filled with `0xffff`s, along with what is probably disk motor control data.
This commit is contained in:
Thomas Harte 2019-05-04 17:29:30 -04:00
parent 98bc570bf7
commit 537b604fc9

View File

@ -98,51 +98,55 @@ class ConcreteMachine:
break; break;
} }
printf("\n"); printf("\n");
} }
} else { } else {
if(cycle.data_select_active()) { if(cycle.data_select_active()) {
uint16_t *memory_base = nullptr; uint16_t *memory_base = nullptr;
bool is_read_only = false;
// When ROM overlay is enabled, the ROM begins at both $000000 and $400000, // When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
// and RAM is available at $600000. // and RAM is available at $600000.
// //
// Otherwise RAM is mapped at $000000 and ROM from $400000. // Otherwise RAM is mapped at $000000 and ROM from $400000.
if((ROM_is_overlay_ && word_address < 0x600000) || (!ROM_is_overlay_ && word_address & 0x200000)) { //
memory_base = rom_.data(); // Writes to the RAM area, at least, seem to go to RAM regardless of the ROM
word_address %= rom_.size(); // overlay setting, so for now I'm gambling below that writes just always go to RAM.
is_read_only = true; if(
} else { !(cycle.operation & Microcycle::Read) ||
(
(ROM_is_overlay_ && word_address >= 0x600000) ||
(!ROM_is_overlay_ && !(word_address & 0x200000))
)
) {
memory_base = ram_.data(); memory_base = ram_.data();
word_address %= ram_.size(); word_address %= ram_.size();
is_read_only = false; } else {
memory_base = rom_.data();
word_address %= rom_.size();
} }
if(!is_read_only || (cycle.operation & Microcycle::Read)) { switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) { default: break;
default: break;
case Microcycle::SelectWord | Microcycle::Read: case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = memory_base[word_address]; cycle.value->full = memory_base[word_address];
break; break;
case Microcycle::SelectByte | Microcycle::Read: case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift()); cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift());
break; break;
case Microcycle::SelectWord: case Microcycle::SelectWord:
memory_base[word_address] = cycle.value->full; memory_base[word_address] = cycle.value->full;
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
memory_base[word_address] = uint16_t( memory_base[word_address] = uint16_t(
(cycle.value->halves.low << cycle.byte_shift()) | (cycle.value->halves.low << cycle.byte_shift()) |
(memory_base[word_address] & (0xffff ^ cycle.byte_mask())) (memory_base[word_address] & (0xffff ^ cycle.byte_mask()))
); );
break; break;
}
} }
} else { } else {
// Add delay if this is a RAM access and video blocks it momentarily. // TODO: add delay if this is a RAM access and video blocks it momentarily.
// "Each [video] fetch took two cycles out of eight"
} }
} }
} }