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https://github.com/TomHarte/CLK.git
synced 2024-07-10 12:29:01 +00:00
It looks like writes should always go to RAM.
Now I see the screen buffer being filled with `0xffff`s, along with what is probably disk motor control data.
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parent
98bc570bf7
commit
537b604fc9
@ -98,29 +98,33 @@ class ConcreteMachine:
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break;
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}
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printf("\n");
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}
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} else {
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if(cycle.data_select_active()) {
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uint16_t *memory_base = nullptr;
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bool is_read_only = false;
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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if((ROM_is_overlay_ && word_address < 0x600000) || (!ROM_is_overlay_ && word_address & 0x200000)) {
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memory_base = rom_.data();
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word_address %= rom_.size();
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is_read_only = true;
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} else {
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//
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// Writes to the RAM area, at least, seem to go to RAM regardless of the ROM
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// overlay setting, so for now I'm gambling below that writes just always go to RAM.
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if(
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!(cycle.operation & Microcycle::Read) ||
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(
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(ROM_is_overlay_ && word_address >= 0x600000) ||
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(!ROM_is_overlay_ && !(word_address & 0x200000))
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)
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) {
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memory_base = ram_.data();
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word_address %= ram_.size();
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is_read_only = false;
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} else {
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memory_base = rom_.data();
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word_address %= rom_.size();
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}
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if(!is_read_only || (cycle.operation & Microcycle::Read)) {
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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default: break;
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@ -140,9 +144,9 @@ class ConcreteMachine:
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);
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break;
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}
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}
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} else {
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// Add delay if this is a RAM access and video blocks it momentarily.
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// TODO: add delay if this is a RAM access and video blocks it momentarily.
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// "Each [video] fetch took two cycles out of eight"
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}
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}
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}
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