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Fix ANDI/ORI/EORI to CCR/SR timing.

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Thomas Harte 2022-05-25 16:20:26 -04:00
parent 4ad0e04c23
commit 56ad6d24ee
1 changed files with 2 additions and 0 deletions
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Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -2018,6 +2018,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// [EORI/ORI/ANDI] #, [CCR/SR]
//
BeginState(LogicalToSR):
IdleBus(4);
// Perform the operation.
PerformDynamic();