From 56ad6d24eed722ef87ca1f35b5851cfb579f78dc Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 16:20:26 -0400
Subject: [PATCH] Fix ANDI/ORI/EORI to CCR/SR timing.

---
 Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 0877055f4..91fb48f81 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -2018,6 +2018,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 		// [EORI/ORI/ANDI] #, [CCR/SR]
 		//
 		BeginState(LogicalToSR):
+			IdleBus(4);
+
 			// Perform the operation.
 			PerformDynamic();