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Shrinks MicroOp struct size from 16 bytes to 4.

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This commit is contained in:
Thomas Harte 2019-07-25 10:14:36 -04:00
parent 9ef1211d53
commit 5769944918
3 changed files with 89 additions and 87 deletions
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107
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -107,7 +107,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
const auto offending_address = *active_step_->microcycle.address;
active_program_ = nullptr;
active_micro_op_ = long_exception_micro_ops_;
active_step_ = active_micro_op_->bus_program;
active_step_ = &all_bus_steps_[active_micro_op_->bus_program];
populate_bus_error_steps(2, get_status(), get_bus_code(), offending_address);
}
}
@ -121,7 +121,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
const auto offending_address = *active_step_->microcycle.address;
active_program_ = nullptr;
active_micro_op_ = long_exception_micro_ops_;
active_step_ = active_micro_op_->bus_program;
active_step_ = &all_bus_steps_[active_micro_op_->bus_program];
populate_bus_error_steps(3, get_status(), get_bus_code(), offending_address);
}
@ -243,7 +243,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
active_program_ = nullptr;
active_micro_op_ = interrupt_micro_ops_;
execution_state_ = ExecutionState::Executing;
active_step_ = active_micro_op_->bus_program;
active_step_ = &all_bus_steps_[active_micro_op_->bus_program];
is_starting_interrupt_ = true;
break;
}
@ -356,13 +356,14 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
}
}
auto bus_program = active_micro_op_->bus_program;
auto bus_program = &all_bus_steps_[active_micro_op_->bus_program];
using int_type = decltype(active_micro_op_->action);
switch(active_micro_op_->action) {
default:
std::cerr << "Unhandled 68000 micro op action " << std::hex << active_micro_op_->action << " within instruction " << decoded_instruction_.full << std::endl;
break;
case int(MicroOp::Action::None): break;
case int_type(MicroOp::Action::None): break;
#define offset_pointer(x) reinterpret_cast<RegisterPair32 *>(&reinterpret_cast<uint8_t *>(static_cast<ProcessorStorage *>(this))[x])
#define source() offset_pointer(active_program_->source_offset)
@ -370,7 +371,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
#define destination() offset_pointer(active_program_->destination_offset)
#define destination_address() address_[active_program_->source_dest & 7]
case int(MicroOp::Action::PerformOperation):
case int_type(MicroOp::Action::PerformOperation):
#define sub_overflow() ((result ^ destination) & (destination ^ source))
#define add_overflow() ((result ^ destination) & ~(destination ^ source))
switch(active_program_->operation) {
@ -970,16 +971,16 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
Divisions.
*/
#define announce_divide_by_zero() \
negative_flag_ = overflow_flag_ = 0; \
zero_result_ = 1; \
active_program_ = nullptr; \
active_micro_op_ = short_exception_micro_ops_; \
bus_program = active_micro_op_->bus_program; \
\
populate_trap_steps(5, get_status()); \
bus_program->microcycle.length = HalfCycles(20); \
\
#define announce_divide_by_zero() \
negative_flag_ = overflow_flag_ = 0; \
zero_result_ = 1; \
active_program_ = nullptr; \
active_micro_op_ = short_exception_micro_ops_; \
bus_program = &all_bus_steps_[active_micro_op_->bus_program]; \
\
populate_trap_steps(5, get_status()); \
bus_program->microcycle.length = HalfCycles(20); \
\
program_counter_.full -= 2;
case Operation::DIVU: {
@ -1890,7 +1891,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
#undef add_overflow
break;
case int(MicroOp::Action::MOVEMtoRComplete): {
case int_type(MicroOp::Action::MOVEMtoRComplete): {
// If this was a word-sized move, perform sign extension.
if(active_program_->operation == Operation::MOVEMtoRw) {
auto mask = next_word_;
@ -1913,7 +1914,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
}
} break;
case int(MicroOp::Action::MOVEMtoMComplete): {
case int_type(MicroOp::Action::MOVEMtoMComplete): {
const auto mode = (decoded_instruction_.full >> 3) & 7;
if(mode == 4) {
const auto reg = decoded_instruction_.full & 7;
@ -1921,7 +1922,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
}
} break;
case int(MicroOp::Action::PrepareJSR): {
case int_type(MicroOp::Action::PrepareJSR): {
const auto mode = (decoded_instruction_.full >> 3) & 7;
// Determine the proper resumption address.
switch(mode) {
@ -1934,25 +1935,25 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
effective_address_[1].full = address_[7].full;
} break;
case int(MicroOp::Action::PrepareBSR):
case int_type(MicroOp::Action::PrepareBSR):
destination_bus_data_[0].full = (decoded_instruction_.full & 0xff) ? program_counter_.full - 2 : program_counter_.full;
address_[7].full -= 4;
effective_address_[1].full = address_[7].full;
break;
case int(MicroOp::Action::PrepareRTS):
case int_type(MicroOp::Action::PrepareRTS):
effective_address_[0].full = address_[7].full;
address_[7].full += 4;
break;
case int(MicroOp::Action::PrepareRTE_RTR):
case int_type(MicroOp::Action::PrepareRTE_RTR):
precomputed_addresses_[0] = address_[7].full + 2;
precomputed_addresses_[1] = address_[7].full;
precomputed_addresses_[2] = address_[7].full + 4;
address_[7].full += 6;
break;
case int(MicroOp::Action::PrepareINT):
case int_type(MicroOp::Action::PrepareINT):
// The INT sequence uses the same storage as the TRAP steps, so this'll get
// the necessary stack work set up.
populate_trap_steps(0, get_status());
@ -1969,7 +1970,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
program_counter_.full -= 4;
break;
case int(MicroOp::Action::PrepareINTVector):
case int_type(MicroOp::Action::PrepareINTVector):
// Let bus error go back to causing exceptions.
is_starting_interrupt_ = false;
@ -1989,7 +1990,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
effective_address_[0].full = uint32_t(source_bus_data_[0].halves.low.halves.low << 2);
break;
case int(MicroOp::Action::CopyNextWord):
case int_type(MicroOp::Action::CopyNextWord):
next_word_ = prefetch_queue_.halves.low.full;
break;
@ -1997,9 +1998,9 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
#define op_add(x, y) x += y
#define op_sub(x, y) x -= y
#define Adjust(op, quantity, effect) \
case int(op) | MicroOp::SourceMask: effect(source_address().full, quantity); break; \
case int(op) | MicroOp::DestinationMask: effect(destination_address().full, quantity); break; \
case int(op) | MicroOp::SourceMask | MicroOp::DestinationMask: \
case int_type(op) | MicroOp::SourceMask: effect(source_address().full, quantity); break; \
case int_type(op) | MicroOp::DestinationMask: effect(destination_address().full, quantity); break; \
case int_type(op) | MicroOp::SourceMask | MicroOp::DestinationMask: \
effect(destination_address().full, quantity); \
effect(source_address().full, quantity); \
break;
@ -2015,7 +2016,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
#undef op_add
#undef op_sub
case int(MicroOp::Action::SignExtendWord):
case int_type(MicroOp::Action::SignExtendWord):
if(active_micro_op_->action & MicroOp::SourceMask) {
source()->halves.high.full =
(source()->halves.low.full & 0x8000) ? 0xffff : 0x0000;
@ -2026,7 +2027,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
}
break;
case int(MicroOp::Action::SignExtendByte):
case int_type(MicroOp::Action::SignExtendByte):
if(active_micro_op_->action & MicroOp::SourceMask) {
source()->full = (source()->full & 0xff) |
(source()->full & 0x80) ? 0xffffff : 0x000000;
@ -2039,32 +2040,32 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
// 16-bit offset addressing modes.
case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask:
case int_type(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask:
// The address the low part of the prefetch queue was read from was two bytes ago, hence
// the subtraction of 2.
effective_address_[0] = u_extend16(prefetch_queue_.halves.low.full) + program_counter_.full - 2;
break;
case int(MicroOp::Action::CalcD16PC) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CalcD16PC) | MicroOp::DestinationMask:
effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + program_counter_.full - 2;
break;
case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask | MicroOp::DestinationMask:
// Similar logic applies here to above, but the high part of the prefetch queue was four bytes
// ago rather than merely two.
effective_address_[0] = u_extend16(prefetch_queue_.halves.high.full) + program_counter_.full - 4;
effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + program_counter_.full - 2;
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
case int_type(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
effective_address_[0] = u_extend16(prefetch_queue_.halves.low.full) + source_address().full;
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address().full;
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
effective_address_[0] = u_extend16(prefetch_queue_.halves.high.full) + source_address().full;
effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address().full;
break;
@ -2080,75 +2081,75 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
target.full += u_extend16(displacement.halves.low.full); \
} \
}
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
case int_type(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
CalculateD8AnXn(prefetch_queue_.halves.low, source_address().full, effective_address_[0]);
} break;
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
case int_type(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_.halves.low, destination_address().full, effective_address_[1]);
} break;
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
case int_type(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_.halves.high, source_address().full, effective_address_[0]);
CalculateD8AnXn(prefetch_queue_.halves.low, destination_address().full, effective_address_[1]);
} break;
case int(MicroOp::Action::CalcD8PCXn) | MicroOp::SourceMask: {
case int_type(MicroOp::Action::CalcD8PCXn) | MicroOp::SourceMask: {
CalculateD8AnXn(prefetch_queue_.halves.low, program_counter_.full - 2, effective_address_[0]);
} break;
case int(MicroOp::Action::CalcD8PCXn) | MicroOp::DestinationMask: {
case int_type(MicroOp::Action::CalcD8PCXn) | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_.halves.low, program_counter_.full - 2, effective_address_[1]);
} break;
case int(MicroOp::Action::CalcD8PCXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
case int_type(MicroOp::Action::CalcD8PCXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_.halves.high, program_counter_.full - 4, effective_address_[0]);
CalculateD8AnXn(prefetch_queue_.halves.low, program_counter_.full - 2, effective_address_[1]);
} break;
#undef CalculateD8AnXn
case int(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask:
case int_type(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask:
effective_address_[0] = u_extend16(prefetch_queue_.halves.low.full);
break;
case int(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask:
effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full);
break;
case int(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask:
case int_type(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask:
effective_address_[0] = prefetch_queue_.full;
break;
case int(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask:
effective_address_[1] = prefetch_queue_.full;
break;
case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask:
case int_type(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask:
source_bus_data_[0] = prefetch_queue_.halves.low.full;
break;
case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask:
destination_bus_data_[0] = prefetch_queue_.halves.low.full;
break;
case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask:
case int_type(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask:
source_bus_data_[0] = prefetch_queue_.full;
break;
case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask:
destination_bus_data_[0] = prefetch_queue_.full;
break;
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask:
case int_type(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask:
effective_address_[0] = source_address();
break;
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::DestinationMask:
effective_address_[1] = destination_address();
break;
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask:
case int_type(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask:
effective_address_[0] = source_address();
effective_address_[1] = destination_address();
break;

48
Processors/68000/Implementation/68000Storage.cpp
View File

@ -473,7 +473,7 @@ struct ProcessorStorageConstructor {
void replace_write_values(ProcessorBase::MicroOp *start, const std::initializer_list<RegisterPair16 *> &values) {
auto value = values.begin();
while(!start->is_terminal()) {
value = replace_write_values(start->bus_program, value);
value = replace_write_values(&storage_.all_bus_steps_[start->bus_program], value);
++start;
}
assert(value == values.end());
@ -827,10 +827,10 @@ struct ProcessorStorageConstructor {
// The arbitrary_base is used so that the offsets returned by assemble_program into
// storage_.all_bus_steps_ can be retained and mapped into the final version of
// storage_.all_bus_steps_ at the end.
BusStep arbitrary_base;
// BusStep arbitrary_base;
#define op(...) storage_.all_micro_ops_.emplace_back(__VA_ARGS__)
#define seq(...) &arbitrary_base + assemble_program(__VA_ARGS__)
#define seq(...) assemble_program(__VA_ARGS__)
#define ea(n) &storage_.effective_address_[n].full
#define a(n) &storage_.address_[n].full
@ -1774,7 +1774,7 @@ struct ProcessorStorageConstructor {
case Ind: // BTST.b Dn, (An)
case PostInc: // BTST.b Dn, (An)+
op(Action::None, seq("nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
if(mode == PostInc) {
op(byte_inc(ea_register) | MicroOp::DestinationMask);
}
@ -1782,7 +1782,7 @@ struct ProcessorStorageConstructor {
case PreDec: // BTST.b Dn, -(An)
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
break;
case XXXl: // BTST.b Dn, (xxx).l
@ -1797,7 +1797,7 @@ struct ProcessorStorageConstructor {
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
seq(pseq("np nrd np", mode), { ea(1) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
break;
case Imm: // BTST.b Dn, #
@ -1836,7 +1836,7 @@ struct ProcessorStorageConstructor {
case Ind: // BTST.b #, (An)
case PostInc: // BTST.b #, (An)+
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
if(mode == PostInc) {
op(byte_inc(ea_register) | MicroOp::DestinationMask);
}
@ -1845,7 +1845,7 @@ struct ProcessorStorageConstructor {
case PreDec: // BTST.b #, -(An)
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : MicroOp::NoBusProgram);
break;
case XXXw: // BTST.b #, (xxx).w
@ -1859,14 +1859,14 @@ struct ProcessorStorageConstructor {
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
seq(pseq("np nrd np", mode), { ea(1) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
break;
case XXXl: // BTST.b #, (xxx).l
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nrd np", { ea(1) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : MicroOp::NoBusProgram);
break;
}
} break;
@ -2452,7 +2452,7 @@ struct ProcessorStorageConstructor {
case XXXl: // PEA (XXX).l
case XXXw: // PEA (XXX).w
op(int(Action::Decrement4) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
op(int(Action::Decrement4) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : MicroOp::NoBusProgram);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
@ -3079,26 +3079,26 @@ struct ProcessorStorageConstructor {
Iterates through the micro-sequence beginning at @c start, finalising bus_program
pointers that have been transiently stored as relative to @c arbitrary_base.
*/
const auto link_operations = [this](MicroOp *start, BusStep *arbitrary_base) {
while(!start->is_terminal()) {
const auto offset = size_t(start->bus_program - arbitrary_base);
assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
start->bus_program = &storage_.all_bus_steps_[offset];
++start;
}
};
// const auto link_operations = [this](MicroOp *start, BusStep *arbitrary_base) {
// while(!start->is_terminal()) {
// const auto offset = size_t(start->bus_program - arbitrary_base);
// assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
// start->bus_program = &storage_.all_bus_steps_[offset];
// ++start;
// }
// };
// Finalise micro-op and program pointers.
for(size_t instruction = 0; instruction < 65536; ++instruction) {
if(micro_op_pointers[instruction] != std::numeric_limits<size_t>::max()) {
storage_.instructions[instruction].micro_operations = uint32_t(micro_op_pointers[instruction]);
link_operations(&storage_.all_micro_ops_[micro_op_pointers[instruction]], &arbitrary_base);
// link_operations(&storage_.all_micro_ops_[micro_op_pointers[instruction]], &arbitrary_base);
}
}
// Link up the interrupt micro ops.
storage_.interrupt_micro_ops_ = &storage_.all_micro_ops_[interrupt_pointer];
link_operations(storage_.interrupt_micro_ops_, &arbitrary_base);
// link_operations(storage_.interrupt_micro_ops_, &arbitrary_base);
std::cout << storage_.all_bus_steps_.size() << " total bus steps" << std::endl;
std::cout << storage_.all_micro_ops_.size() << " total micro ops" << std::endl;
@ -3249,7 +3249,7 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
//
// Assumed order of input: PC.h, SR, PC.l (i.e. the opposite of TRAP's output).
for(const int instruction: { 0x4e73, 0x4e77 }) {
auto steps = all_micro_ops_[instructions[instruction].micro_operations].bus_program;
auto steps = &all_bus_steps_[all_micro_ops_[instructions[instruction].micro_operations].bus_program];
steps[0].microcycle.value = steps[1].microcycle.value = &program_counter_.halves.high;
steps[4].microcycle.value = steps[5].microcycle.value = &program_counter_.halves.low;
}
@ -3259,10 +3259,10 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
// Complete linkage of the exception micro program.
short_exception_micro_ops_ = &all_micro_ops_[short_exception_offset];
short_exception_micro_ops_->bus_program = trap_steps_;
short_exception_micro_ops_->bus_program = trap_offset;
long_exception_micro_ops_ = &all_micro_ops_[long_exception_offset];
long_exception_micro_ops_->bus_program = bus_error_steps_;
long_exception_micro_ops_->bus_program = bus_error_offset;
// Set initial state.
active_step_ = reset_bus_steps_;

21
Processors/68000/Implementation/68000Storage.hpp
View File

@ -216,7 +216,7 @@ class ProcessorStorage {
be performed.
*/
struct MicroOp {
enum class Action: int {
enum class Action: uint8_t {
None,
/// Does whatever this instruction says is the main operation.
@ -312,21 +312,22 @@ class ProcessorStorage {
// steps detail appropriately.
PrepareINTVector,
};
static const int SourceMask = 1 << 30;
static const int DestinationMask = 1 << 29;
int action = int(Action::None);
static const int SourceMask = 1 << 7;
static const int DestinationMask = 1 << 6;
uint8_t action = uint8_t(Action::None);
BusStep *bus_program = nullptr;
static const uint16_t NoBusProgram = std::numeric_limits<uint16_t>::max();
uint16_t bus_program = NoBusProgram;
MicroOp() {}
MicroOp(int action) : action(action) {}
MicroOp(int action, BusStep *bus_program) : action(action), bus_program(bus_program) {}
MicroOp(uint8_t action) : action(action) {}
MicroOp(uint8_t action, uint16_t bus_program) : action(action), bus_program(bus_program) {}
MicroOp(Action action) : MicroOp(int(action)) {}
MicroOp(Action action, BusStep *bus_program) : MicroOp(int(action), bus_program) {}
MicroOp(Action action) : MicroOp(uint8_t(action)) {}
MicroOp(Action action, uint16_t bus_program) : MicroOp(uint8_t(action), bus_program) {}
forceinline bool is_terminal() const {
return bus_program == nullptr;
return bus_program == std::numeric_limits<uint16_t>::max();
}
};