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Start dealing with per-instruction fields.
This commit is contained in:
Thomas Harte
parent
d639dc8bcb
commit
57b45076c5
@ -16,38 +16,47 @@
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namespace InstructionSet::ARM {
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template <Model model>
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using OperationTable = std::array<Operation, 128>;
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using OperationTable = std::array<Operation, 256>;
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template <Model model>
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constexpr OperationTable<model> operation_table() {
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OperationTable<model> result{};
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for(std::size_t c = 0; c < result.size(); c++) {
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const auto opcode = static_cast<uint32_t>(c << 21);
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const auto opcode = static_cast<uint32_t>(c << 20);
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// Cf. the ARM2 datasheet, p45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case.
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// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case. More specific
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// page references are provided were more detailed versions of the
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// decoding are depicted.
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// Data processing; cf. p.17.
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if(((opcode >> 26) & 0b11) == 0b00) {
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result[c] = Operation((c >> 21) & 0xf);
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continue;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if(((opcode >> 22) & 0b111'111) == 0b000'000) {
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result[c] =
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((opcode >> 21) & 1) ? Operation::MLA : Operation::MUL;
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continue;
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if(((opcode >> 26) & 0b11) == 0b01) {
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result[c] = Operation::SingleDataTransfer;
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result[c] =
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((opcode >> 20) & 1) ? Operation::LDR : Operation::STR;
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continue;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if(((opcode >> 25) & 0b111) == 0b100) {
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result[c] = Operation::BlockDataTransfer;
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result[c] =
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((opcode >> 20) & 1) ? Operation::LDM : Operation::STM;
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continue;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if(((opcode >> 25) & 0b111) == 0b101) {
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result[c] =
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((opcode >> 24) & 1) ? Operation::BL : Operation::B;
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@ -77,7 +86,19 @@ constexpr OperationTable<model> operation_table() {
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template <Model model>
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constexpr Operation operation(uint32_t opcode) {
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constexpr OperationTable<model> operations = operation_table<model>();
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return operations[(opcode >> 21) & 0x7f];
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const auto op = operations[(opcode >> 21) & 0x7f];
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// MUL and MLA have an extra constraint that doesn't fit the neat
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// 256-entry table format as above.
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if(
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(op == Operation::MUL || op == Operation::MLA)
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&& ((opcode >> 4) & 0b1111) != 0b1001
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) {
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return Operation::Undefined;
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}
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return op;
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}
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}
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@ -14,6 +14,13 @@
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namespace InstructionSet::ARM {
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enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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ArithmeticRight = 0b10,
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RotateRight = 0b11,
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};
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template <Model model>
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class Instruction {
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public:
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@ -24,8 +31,61 @@ class Instruction {
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return InstructionSet::ARM::operation<model>(opcode_);
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}
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//
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// B and BL.
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//
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/// Provides a 26-bit offset to add to the program counter for B and BL.
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uint32_t b_offset() const { return (opcode_ & 0xff'ffff) << 2; }
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//
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// Data processing (i.e. AND to MVN).
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//
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/// @returns @c true if this operation should set condition codes; @c false otherwise.
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/// @note Valid for data processing and multiply/multiply-accumulate.
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bool set_condition_codes() const { return opcode_ & (1 << 20); }
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// TODO: could build this into the Operation?
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/// The destination register index.
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int destination() const { return (opcode_ >> 12) & 0xf; }
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/// The operand 1 register index.
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int operand1() const { return (opcode_ >> 16) & 0xf; }
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/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
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/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
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bool operand2_is_immediate() const { return opcode_ & (1 << 25); }
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//
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// Register values for operand 2.
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//
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/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
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int operand2() const { return opcode_ & 0xf; }
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/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
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ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
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/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
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bool shift_count_is_register() const { return opcode_ & (1 << 4); }
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/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
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int shift_register() const { return (opcode_ >> 8) & 0xf; }
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/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
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int shift_amount() const { return (opcode_ >> 7) & 0x1f; }
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//
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// Immediate values for operand 2.
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//
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/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int immediate() const { return opcode_ & 0xff; }
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/// The number of bits to rotate @c immediate() by if @c operand2_is_immediate() is @c true; meaningless otherwise.
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int rotate() const { return (opcode_ >> 7) & 0x1e; }
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private:
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uint32_t opcode_;
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};
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// TODO: do MUL and MLA really transpose Rd and Rn as per the data sheet?
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// ARM: Assembly Language Programming by Cockerell thinks not.
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}
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@ -11,16 +11,44 @@
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namespace InstructionSet::ARM {
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enum class Operation {
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AND, EOR, SUB, RSB,
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ADD, ADC, SBC, RSC,
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TST, TEQ, CMP, CMN,
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ORR, MOV, BIC, MVN,
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/// Rd = Op1 AND Op2.
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AND,
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/// Rd = Op1 EOR Op2.
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EOR,
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/// Rd = Op1 - Op2.
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SUB,
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/// Rd = Op2 - Op1.
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RSB,
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/// Rd = Op1 + Op2.
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ADD,
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/// Rd = Op1 + Ord2 + C.
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ADC,
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/// Rd = Op1 - Op2 + C.
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SBC,
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/// Rd = Op2 - Op1 + C.
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RSC,
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/// Set condition codes on Op1 AND Op2.
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TST,
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/// Set condition codes on Op1 EOR Op2.
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TEQ,
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/// Set condition codes on Op1 - Op2.
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CMP,
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/// Set condition codes on Op1 + Op2.
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CMN,
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/// Rd = Op1 OR Op2.
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ORR,
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/// Rd = Op2
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MOV,
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/// Rd = Op1 AND NOT Op2.
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BIC,
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/// Rd = NOT Op2.
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MVN,
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B, BL,
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MUL, MLA,
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SingleDataTransfer, // TODO: LDR or STR?
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BlockDataTransfer, // TODO: LDM or STM?
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LDR, STR,
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LDM, STM,
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SoftwareInterrupt,
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CoprocessorDataOperationOrRegisterTransfer,
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