1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 23:32:28 +00:00

So, provisionally: this looks like (i) the one cycle to write; plus (ii) the number of cycles to get to the end of the pixels (which is _horizontalTimer+1 for me because _horizontalTimer = 0 is a pixel); plus (iii) one cycle of latency to wake up. Am I making that up? Time will tell.

This commit is contained in:
Thomas Harte 2015-07-30 15:49:38 -04:00
parent f5475369d6
commit 58908b60ac

View File

@ -217,8 +217,8 @@ int Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t add
case 0x01: _vBlankEnabled = !!(*value & 0x02); break; case 0x01: _vBlankEnabled = !!(*value & 0x02); break;
case 0x02: { case 0x02: {
cycle_count += (_horizontalTimer / 3)+1; cycle_count += ((_horizontalTimer+4) / 3);
output_pixels(_horizontalTimer+3); output_pixels(_horizontalTimer+4);
} break; } break;
case 0x03: _horizontalTimer = 227; break; case 0x03: _horizontalTimer = 227; break;