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Implement CBW, CLC, CLD, CLI, CMC.

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This commit is contained in:
Thomas Harte
2023-10-09 11:59:38 -04:00
parent 769aed10ea
commit 59521f9d38
2 changed files with 24 additions and 5 deletions
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24
InstructionSets/x86/Implementation/PerformImplementation.hpp
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@@ -358,7 +358,7 @@ inline void call_absolute(IntT target, FlowControllerT &flow_controller) {
} }
template <Model model, typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT> template <Model model, typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT>
inline void call_far(InstructionT &instruction, void call_far(InstructionT &instruction,
FlowControllerT &flow_controller, FlowControllerT &flow_controller,
RegistersT &registers, RegistersT &registers,
MemoryT &memory) { MemoryT &memory) {
@@ -389,6 +389,15 @@ inline void call_far(InstructionT &instruction,
flow_controller.call(segment, offset); flow_controller.call(segment, offset);
} }
inline void cbw(CPU::RegisterPair16 &ax) {
ax.halves.high = (ax.halves.low & 0x80) ? 0xff : 0x00;
}
inline void clc(Status &status) { status.carry = 0; }
inline void cld(Status &status) { status.direction = 0; }
inline void cli(Status &status) { status.interrupt = 0; } // TODO: quite a bit more in protected mode.
inline void cmc(Status &status) { status.carry = !status.carry; }
} }
template < template <
@@ -447,10 +456,9 @@ template <
case Operation::AAM: Primitive::aam(registers.axp(), instruction.operand(), status, flow_controller); return; case Operation::AAM: Primitive::aam(registers.axp(), instruction.operand(), status, flow_controller); return;
case Operation::AAS: Primitive::aas(registers.axp(), status); return; case Operation::AAS: Primitive::aas(registers.axp(), status); return;
case Operation::ADC: Primitive::adc(destination(), source(), status); break; case Operation::ADC: Primitive::adc(destination(), source(), status); break;
case Operation::ADD: Primitive::add(destination(), source(), status); break; case Operation::ADD: Primitive::add(destination(), source(), status); break;
case Operation::AND: Primitive::and_(destination(), source(), status); break;
case Operation::AND: Primitive::and_(destination(), source(), status); break;
case Operation::CALLrel: case Operation::CALLrel:
Primitive::call_relative(instruction.displacement(), registers, flow_controller); Primitive::call_relative(instruction.displacement(), registers, flow_controller);
@@ -461,6 +469,12 @@ template <
case Operation::CALLfar: case Operation::CALLfar:
Primitive::call_far<model>(instruction, flow_controller, registers, memory); Primitive::call_far<model>(instruction, flow_controller, registers, memory);
return; return;
case Operation::CBW: Primitive::cbw(registers.axp()); return;
case Operation::CLC: Primitive::clc(status); return;
case Operation::CLD: Primitive::cld(status); return;
case Operation::CLI: Primitive::cli(status); return;
case Operation::CMC: Primitive::cmc(status); return;
} }
// Write to memory if required to complete this operation. // Write to memory if required to complete this operation.

5
OSBindings/Mac/Clock SignalTests/8088Tests.mm
View File

@@ -295,6 +295,11 @@ struct FailedExecution {
@"3F.json.gz", // AAS @"3F.json.gz", // AAS
@"D4.json.gz", // AAM @"D4.json.gz", // AAM
@"D5.json.gz", // AAD @"D5.json.gz", // AAD
@"98.json.gz", // CBW
@"F8.json.gz", // CLC
@"FC.json.gz", // CLD
@"FA.json.gz", // CLI
@"F5.json.gz", // CMC
]]; ]];
NSSet *ignoreList = nil; NSSet *ignoreList = nil;