From 5998f3b35b19906744f44815f583db13ac5fa4fd Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Tue, 13 Apr 2021 20:00:18 -0400
Subject: [PATCH] Corrects LD[I/D/IR/DR] timing.
Macro cleanup to come.
---
Processors/Z80/Implementation/Z80Storage.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Processors/Z80/Implementation/Z80Storage.cpp b/Processors/Z80/Implementation/Z80Storage.cpp
index a0519a279..b290110c3 100644
--- a/Processors/Z80/Implementation/Z80Storage.cpp
+++ b/Processors/Z80/Implementation/Z80Storage.cpp
@@ -60,7 +60,7 @@ ProcessorStorage::ProcessorStorage() {
#define Read5(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)), InternalOperation(4)
#define Write3(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val))
-#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(4, addr, val, false)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val))
+#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val)), InternalOperation(4)
#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))