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Fix trans for instruction fetches.

This commit is contained in:
Thomas Harte 2024-04-29 21:54:59 -04:00
parent b66d69b60c
commit 5a84e98256
3 changed files with 8 additions and 3 deletions
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2
InstructionSets/ARM/Registers.hpp
View File

@ -231,7 +231,7 @@ struct Registers {
// MARK: - Condition tests.
/// @returns @c true if @c condition tests as true; @c false otherwise.
bool test(Condition condition) {
bool test(Condition condition) const {
const auto ne = [&]() -> bool {
return zero_result_;
};

2
Machines/Acorn/Archimedes/Archimedes.cpp
View File

@ -549,7 +549,7 @@ class ConcreteMachine:
uint32_t advance_pipeline(uint32_t pc) {
uint32_t instruction = 0; // Value should never be used; this avoids a spurious GCC warning.
const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode() == InstructionSet::ARM::Mode::User);
return pipeline_.exchange(
did_read ? instruction : Pipeline::SWI,
did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);

7
Machines/Acorn/Archimedes/MemoryController.hpp
View File

@ -173,7 +173,7 @@ struct MemoryController {
}
template <typename IntT>
bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
bool read(uint32_t address, IntT &source, bool trans) {
switch (read_zones_[(address >> 21) & 31]) {
case Zone::PhysicallyMappedRAM:
if(trans) return false;
@ -212,6 +212,11 @@ struct MemoryController {
return true;
}
template <typename IntT>
bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
return read(address, source, trans);
}
//
// Expose various IOC-owned things.
//