diff --git a/OSBindings/Mac/Clock SignalTests/65816kromTests.swift b/OSBindings/Mac/Clock SignalTests/65816kromTests.swift
index eaefc0cb7..023dee997 100644
--- a/OSBindings/Mac/Clock SignalTests/65816kromTests.swift	
+++ b/OSBindings/Mac/Clock SignalTests/65816kromTests.swift	
@@ -52,6 +52,9 @@ class Krom65816Tests: XCTestCase {
 		machine.setValue(0x00ff, for: .stackPointer)
 		machine.setValue(0x34, for: .flags)
 
+		// There seems to be some Nintendo-special register at address 0x0000.
+		machine.setValue(0xb5, forAddress: 0x0000)
+
 		// Poke some fixed values for SNES registers to get past initial setup.
 		machine.setValue(0x42, forAddress: 0x4210)	// "RDNMI", apparently; this says: CPU version 2, vblank interrupt request.
 		var allowNegativeError = false
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index 549baef4e..e308352b4 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -435,7 +435,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
 							data_address_ = registers_.emulation_flag ? 0xfffe : 0xffe6;
 						} else {
 							// Implicitly: COP.
-							data_address_ = registers_.emulation_flag ? 0xfff4 : 0xffe8;
+							data_address_ = registers_.emulation_flag ? 0xfff4 : 0xffe4;
 						}
 					}
 
@@ -545,7 +545,9 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
 							}
 						break;
 
-						case NOP:	break;
+						case NOP:						break;
+						case WDM:	++registers_.pc;	break;
+
 
 						// The below attempt to obey the 8/16-bit mixed transfer rules
 						// as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index b2a1ffbb4..e7810785e 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -867,7 +867,7 @@ ProcessorStorage::ProcessorStorage() {
 
 	/* 0x40 RTI s */			op(stack_rti, RTI);
 	/* 0x41	EOR (d, x) */		op(direct_indexed_indirect, EOR);
-	/* 0x42	WDM i */			op(implied, NOP);
+	/* 0x42	WDM i */			op(implied, WDM);
 	/* 0x43	EOR d, s */			op(stack_relative, EOR);
 	/* 0x44	MVP xyc */			op(block_move, MVP);
 	/* 0x45	EOR d */			op(direct, EOR);
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index b85578007..81b905755 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -193,7 +193,7 @@ enum Operation: uint8_t {
 	// These are all implicit.
 	CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI,
 	TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX,
-	XCE, XBA,
+	XCE, XBA, WDM,
 
 	STP, WAI,