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Fixes COP vector, ensures WDM skips a byte.

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This commit is contained in:
Thomas Harte
2020-11-03 20:01:02 -05:00
parent 91ea2eff4c
commit 5cbb91f352
4 changed files with 9 additions and 4 deletions
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3
OSBindings/Mac/Clock SignalTests/65816kromTests.swift
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@@ -52,6 +52,9 @@ class Krom65816Tests: XCTestCase {
machine.setValue(0x00ff, for: .stackPointer) machine.setValue(0x00ff, for: .stackPointer)
machine.setValue(0x34, for: .flags) machine.setValue(0x34, for: .flags)
// There seems to be some Nintendo-special register at address 0x0000.
machine.setValue(0xb5, forAddress: 0x0000)
// Poke some fixed values for SNES registers to get past initial setup. // Poke some fixed values for SNES registers to get past initial setup.
machine.setValue(0x42, forAddress: 0x4210) // "RDNMI", apparently; this says: CPU version 2, vblank interrupt request. machine.setValue(0x42, forAddress: 0x4210) // "RDNMI", apparently; this says: CPU version 2, vblank interrupt request.
var allowNegativeError = false var allowNegativeError = false

6
Processors/65816/Implementation/65816Implementation.hpp
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@@ -435,7 +435,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
data_address_ = registers_.emulation_flag ? 0xfffe : 0xffe6; data_address_ = registers_.emulation_flag ? 0xfffe : 0xffe6;
} else { } else {
// Implicitly: COP. // Implicitly: COP.
data_address_ = registers_.emulation_flag ? 0xfff4 : 0xffe8; data_address_ = registers_.emulation_flag ? 0xfff4 : 0xffe4;
} }
} }
@@ -545,7 +545,9 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
} }
break; break;
case NOP: break; case NOP: break;
case WDM: ++registers_.pc; break;
// The below attempt to obey the 8/16-bit mixed transfer rules // The below attempt to obey the 8/16-bit mixed transfer rules
// as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM // as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM

2
Processors/65816/Implementation/65816Storage.cpp
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@@ -867,7 +867,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x40 RTI s */ op(stack_rti, RTI); /* 0x40 RTI s */ op(stack_rti, RTI);
/* 0x41 EOR (d, x) */ op(direct_indexed_indirect, EOR); /* 0x41 EOR (d, x) */ op(direct_indexed_indirect, EOR);
/* 0x42 WDM i */ op(implied, NOP); /* 0x42 WDM i */ op(implied, WDM);
/* 0x43 EOR d, s */ op(stack_relative, EOR); /* 0x43 EOR d, s */ op(stack_relative, EOR);
/* 0x44 MVP xyc */ op(block_move, MVP); /* 0x44 MVP xyc */ op(block_move, MVP);
/* 0x45 EOR d */ op(direct, EOR); /* 0x45 EOR d */ op(direct, EOR);

2
Processors/65816/Implementation/65816Storage.hpp
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@@ -193,7 +193,7 @@ enum Operation: uint8_t {
// These are all implicit. // These are all implicit.
CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI,
TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX, TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX,
XCE, XBA, XCE, XBA, WDM,
STP, WAI, STP, WAI,