diff --git a/Components/9918/Implementation/9918.cpp b/Components/9918/Implementation/9918.cpp index 9f70ad174..e75bae6b6 100644 --- a/Components/9918/Implementation/9918.cpp +++ b/Components/9918/Implementation/9918.cpp @@ -22,16 +22,6 @@ namespace { constexpr unsigned int CRTCyclesPerLine = 1365; constexpr unsigned int CRTCyclesDivider = 4; -template constexpr int vram_access_delay() { - // This seems to be correct for all currently-modelled VDPs; - // it's the delay between an external device scheduling a - // read or write and the very first time that can occur - // (though, in practice, it won't happen until the next - // external slot after this number of cycles after the - // device has requested the read or write). - return 6; -} - } template @@ -500,7 +490,7 @@ void TMS9918::write(int address, uint8_t value) { // Enqueue the write to occur at the next available slot. this->read_ahead_buffer_ = value; this->queued_access_ = MemoryAccess::Write; - this->cycles_until_access_ = vram_access_delay(); + this->cycles_until_access_ = Timing::VRAMAccessDelay; return; } @@ -615,7 +605,7 @@ void TMS9918::write(int address, uint8_t value) { // A read request is enqueued upon setting the address; conversely a write // won't be enqueued unless and until some actual data is supplied. this->queued_access_ = MemoryAccess::Read; - this->cycles_until_access_ = vram_access_delay(); + this->cycles_until_access_ = Timing::VRAMAccessDelay; } this->master_system_.cram_is_selected = false; } diff --git a/Components/9918/Implementation/ClockConverter.hpp b/Components/9918/Implementation/ClockConverter.hpp index a81db17f3..b582d5d99 100644 --- a/Components/9918/Implementation/ClockConverter.hpp +++ b/Components/9918/Implementation/ClockConverter.hpp @@ -21,16 +21,19 @@ template struct Timing {}; template struct Timing> { constexpr static int CyclesPerLine = 1368; + constexpr static int VRAMAccessDelay = 6; }; template struct Timing> { constexpr static int CyclesPerLine = 342; + constexpr static int VRAMAccessDelay = 6; }; template <> struct Timing { constexpr static int CyclesPerLine = 3420; + constexpr static int VRAMAccessDelay = 6; }; constexpr int TMSAccessWindowsPerLine = 171; diff --git a/Components/9918/Implementation/PersonalityTraits.hpp b/Components/9918/Implementation/PersonalityTraits.hpp index 18fae4319..7ce18f7a7 100644 --- a/Components/9918/Implementation/PersonalityTraits.hpp +++ b/Components/9918/Implementation/PersonalityTraits.hpp @@ -21,6 +21,7 @@ constexpr bool is_yamaha_vdp(Personality p) { return p == Personality::V9938 || p == Personality::V9958; } +// i.e. one with the original internal timings. constexpr bool is_classic_vdp(Personality p) { return p == Personality::TMS9918A ||