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Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
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@ -97,7 +97,7 @@ void ACIA::run_for(HalfCycles length) {
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const auto write_data_time_remaining = transmit.write_data_time_remaining();
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const auto write_data_time_remaining = transmit.write_data_time_remaining();
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if(write_data_time_remaining) {
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if(write_data_time_remaining) {
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if(transmit_advance > write_data_time_remaining) {
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if(transmit_advance >= write_data_time_remaining) {
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if(next_transmission_ != NoTransmission) {
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if(next_transmission_ != NoTransmission) {
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transmit.flush_writing();
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transmit.flush_writing();
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consider_transmission();
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consider_transmission();
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@ -142,7 +142,7 @@ void ACIA::consider_transmission() {
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// Output all that.
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// Output all that.
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const int total_bits = 1 + data_bits_ + stop_bits_ + (parity_ != Parity::None);
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const int total_bits = 1 + data_bits_ + stop_bits_ + (parity_ != Parity::None);
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transmit.write(divider_, total_bits, transmission);
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transmit.write(divider_ * 2, total_bits, transmission);
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// Mark the transmit register as empty again.
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// Mark the transmit register as empty again.
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next_transmission_ = NoTransmission;
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next_transmission_ = NoTransmission;
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