diff --git a/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift b/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift
index d2d4f5107..b030bd6a5 100644
--- a/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift	
+++ b/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift	
@@ -95,6 +95,8 @@ class KlausDormannTests: XCTestCase {
 				case 0x1d88: return "TRB set Z flag incorrectly"
 				case 0x1e7c: return "RMB set flags incorrectly"
 
+				case 0x2245: return "CMP (zero) didn't work"
+
 				case 0: return "Didn't find tests"
 				default: return "Unknown error at \(String(format:"%04x", address))"
 			}
diff --git a/Processors/6502/Implementation/6502Implementation.hpp b/Processors/6502/Implementation/6502Implementation.hpp
index b8a52f2e6..771b4b5d2 100644
--- a/Processors/6502/Implementation/6502Implementation.hpp
+++ b/Processors/6502/Implementation/6502Implementation.hpp
@@ -253,6 +253,15 @@ if(number_of_cycles <= Cycles(0)) break;
 						operand_ |= a_;
 					continue;
 
+// MARK: - RMB and SMB
+
+					case OperationRMB:
+						operand_ &= ~(1 << (operation_ >> 4));
+					continue;
+					case OperationSMB:
+						operand_ |= 1 << ((operation_ >> 4)&7);
+					continue;
+
 // MARK: - ADC/SBC (and INS)
 
 					case OperationINS:
diff --git a/Processors/6502/Implementation/6502Storage.cpp b/Processors/6502/Implementation/6502Storage.cpp
index 7ef8ae728..d8fae7c4f 100644
--- a/Processors/6502/Implementation/6502Storage.cpp
+++ b/Processors/6502/Implementation/6502Storage.cpp
@@ -285,7 +285,7 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
 		Install(0x92, ZeroIndirectWrite(OperationSTA));
 		Install(0xb2, ZeroIndirectRead(OperationLDA));
 		Install(0xd2, ZeroIndirectRead(OperationCMP));
-		Install(0xd2, ZeroIndirectRead(OperationSBC));
+		Install(0xf2, ZeroIndirectRead(OperationSBC));
 
 		// Add STZ.
 		Install(0x9c, AbsoluteWrite(OperationSTZ));
@@ -303,6 +303,14 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
 		Install(0x0c, AbsoluteReadModifyWrite(OperationTSB));
 		Install(0x14, ZeroReadModifyWrite(OperationTRB));
 		Install(0x1c, AbsoluteReadModifyWrite(OperationTRB));
+
+		// Add RMB and SMB.
+		for(int c = 0x07; c <= 0x77; c += 0x10) {
+			Install(c, ZeroReadModifyWrite(OperationRMB));
+		}
+		for(int c = 0x87; c <= 0xf7; c += 0x10) {
+			Install(c, ZeroReadModifyWrite(OperationSMB));
+		}
 	}
 #undef Install
 }
diff --git a/Processors/6502/Implementation/6502Storage.hpp b/Processors/6502/Implementation/6502Storage.hpp
index 8e41934ea..85d4d1f3d 100644
--- a/Processors/6502/Implementation/6502Storage.hpp
+++ b/Processors/6502/Implementation/6502Storage.hpp
@@ -53,7 +53,7 @@ class ProcessorStorage {
 			OperationSAX,								OperationSHA,
 			OperationSHX,								OperationSHY,						OperationSHS,							OperationCMP,
 			OperationCPX,								OperationCPY,						OperationBIT,							OperationBITNoNV,
-			OperationASL,
+			OperationASL,								OperationRMB,						OperationSMB,
 			OperationASO,								OperationROL,						OperationRLA,							OperationLSR,
 			OperationLSE,								OperationASR,						OperationROR,							OperationRRA,
 			OperationCLC,								OperationCLI,						OperationCLV,							OperationCLD,