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https://github.com/TomHarte/CLK.git
synced 2025-01-14 13:33:42 +00:00
Switches to table-based address decoding.
This commit is contained in:
Thomas Harte
parent
83393e8e91
commit
5e76d593af
@ -131,6 +131,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// Insert any supplied media.
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insert_media(target.media);
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// Set the immutables of the memory map.
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setup_memory_map();
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}
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~ConcreteMachine() {
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@ -172,13 +175,20 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// a read or write.
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if(!cycle.data_select_active()) return delay;
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// Check whether this access maps into the IO area; if so then
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// apply more complicated decoding logic.
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if(word_address >= 0x400000) {
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const int register_address = word_address >> 8;
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uint16_t *memory_base = nullptr;
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switch(memory_map_[word_address >> 18]) {
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default: break;
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case BusDevice::Unassigned:
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fill_unmapped(cycle);
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return delay;
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case BusDevice::VIA: {
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if(*cycle.address & 1) {
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fill_unmapped(cycle);
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} else {
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const int register_address = word_address >> 8;
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switch(word_address & 0x78f000) {
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case 0x70f000:
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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@ -186,9 +196,23 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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} else {
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via_.set_register(register_address, cycle.value->halves.low);
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}
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break;
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case 0x68f000:
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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} return delay;
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case BusDevice::PhaseRead: {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} return delay;
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case BusDevice::IWM: {
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if(*cycle.address & 1) {
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const int register_address = word_address >> 8;
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// The IWM; this is a purely polled device, so can be run on demand.
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iwm_.flush();
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if(cycle.operation & Microcycle::Read) {
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@ -196,101 +220,79 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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} else {
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iwm_.iwm.write(register_address, cycle.value->halves.low);
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}
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break;
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case 0x780000:
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// Phase read.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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}
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break;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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fill_unmapped(cycle);
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}
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} return delay;
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case 0x480000: case 0x48f000:
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case 0x580000: case 0x58f000:
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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++phase_;
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case BusDevice::SCCReadResetPhase: {
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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adjust_phase();
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} else {
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// A0 = 1 => reset; A0 = 0 => read.
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if(*cycle.address & 1) {
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scc_.reset();
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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}
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} else {
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if(word_address < 0x500000) {
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// A0 = 1 => reset; A0 = 0 => read.
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if(*cycle.address & 1) {
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scc_.reset();
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} else {
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const auto read = scc_.read(int(word_address));
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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}
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}
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} else {
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(word_address), 0xff);
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} else {
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scc_.write(int(word_address), cycle.value->halves.low);
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}
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}
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const auto read = scc_.read(int(word_address));
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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}
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}
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break;
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default:
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if(cycle.operation & Microcycle::Read) {
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LOG("Unrecognised read " << PADHEX(6) << (*cycle.address & 0xffffff));
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cycle.value->halves.low = 0x00;
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} else {
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LOG("Unrecognised write %06x" << PADHEX(6) << (*cycle.address & 0xffffff));
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}
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break;
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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return delay;
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}
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// Having reached here, this is a RAM or ROM access.
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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uint16_t *memory_base;
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if(
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(!ROM_is_overlay_ && word_address < 0x200000) ||
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(ROM_is_overlay_ && word_address >= 0x300000)
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) {
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memory_base = ram_;
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word_address &= ram_mask_;
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// This is coupled with the Macintosh implementation of video; the magic
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// constant should probably be factored into the Video class.
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// It embodies knowledge of the fact that video (and audio) will always
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// be fetched from the final $d900 bytes (i.e. $6c80 words) of memory.
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// (And that ram_mask_ = ram size - 1).
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if(word_address > ram_mask_ - 0x6c80)
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update_video();
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} else {
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memory_base = rom_;
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word_address &= rom_mask_;
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// Writes to ROM have no effect, and it doesn't mirror above 0x60000.
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if(!(cycle.operation & Microcycle::Read)) return delay;
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if(word_address >= 0x300000) {
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if(cycle.operation & Microcycle::SelectWord) {
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cycle.value->full = 0xffff;
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} else {
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cycle.value->halves.low = 0xff;
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}
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return delay;
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}
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} return delay;
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case BusDevice::SCCWrite: {
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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adjust_phase();
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} else {
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(word_address), 0xff);
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cycle.value->halves.low = 0xff;
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} else {
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scc_.write(int(word_address), cycle.value->halves.low);
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}
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} else {
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fill_unmapped(cycle);
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}
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}
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} return delay;
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case BusDevice::RAM: {
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// This is coupled with the Macintosh implementation of video; the magic
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// constant should probably be factored into the Video class.
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// It embodies knowledge of the fact that video (and audio) will always
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// be fetched from the final $d900 bytes (i.e. $6c80 words) of memory.
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// (And that ram_mask_ = ram size - 1).
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if(word_address > ram_mask_ - 0x6c80)
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update_video();
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memory_base = ram_;
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word_address &= ram_mask_;
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} break;
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case BusDevice::ROM: {
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if(!(cycle.operation & Microcycle::Read)) return delay;
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memory_base = rom_;
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word_address &= rom_mask_;
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} break;
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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// TODO: interrupt acknowledge cycles also end up here, which may suggest the 68000 is loading the address bus
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// incorrectly during interrupt acknowledgment cycles. Check.
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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default:
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break;
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// Catches the deliberation set of operation to 0 above.
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case 0: break;
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case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
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// The Macintosh uses autovectored interrupts.
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mc68000_.set_is_peripheral_address(true);
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@ -313,17 +315,6 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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break;
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}
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/*
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Normal memory map:
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000000: RAM
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400000: ROM
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9FFFF8+: SCC read operations
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BFFFF8+: SCC write operations
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DFE1FF+: IWM
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EFE1FE+: VIA
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*/
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return delay;
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}
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@ -344,6 +335,21 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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void set_rom_is_overlay(bool rom_is_overlay) {
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ROM_is_overlay_ = rom_is_overlay;
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populate_memory_map([rom_is_overlay] (std::function<void(int target, BusDevice device)> map_to) {
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// Addresses up to $80 0000 aren't affected by this bit.
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if(rom_is_overlay) {
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// Up to $60 0000 mirrors of the ROM alternate with unassigned areas every $10 0000 byes.
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for(int c = 0; c <= 0x600000; c += 0x100000) {
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map_to(c, ((c >> 20)&1) ? BusDevice::ROM : BusDevice::Unassigned);
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}
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map_to(0x800000, BusDevice::RAM);
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} else {
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map_to(0x400000, BusDevice::RAM);
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map_to(0x500000, BusDevice::ROM);
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map_to(0x800000, BusDevice::Unassigned);
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}
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});
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}
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bool video_is_outputting() {
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@ -406,6 +412,19 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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}
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private:
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forceinline void adjust_phase() {
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++phase_;
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}
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forceinline void fill_unmapped(const Microcycle &cycle) {
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if(!(cycle.operation & Microcycle::Read)) return;
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if(cycle.operation & Microcycle::SelectWord) {
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cycle.value->full = 0xffff;
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} else {
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cycle.value->halves.low = 0xff;
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}
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}
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/// Advances all non-CPU components by @c duration half cycles.
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forceinline void run_for(HalfCycles duration) {
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time_since_video_update_ += duration;
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@ -640,6 +659,66 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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Apple::Macintosh::KeyboardMapper keyboard_mapper_;
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enum class BusDevice {
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RAM, ROM, VIA, IWM, SCCWrite, SCCReadResetPhase, SCSI, PhaseRead, Unassigned
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};
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/// Divides the 24-bit address space up into $80000 (i.e. 512kb) segments, recording
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/// which device is current mapped in each area. Keeping it in a table is a bit faster
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/// than the multi-level address inspection that is otherwise required, as well as
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/// simplifying slightly the handling of different models.
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///
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/// So: index with the top 5 bits of the 24-bit address.
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BusDevice memory_map_[32];
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void setup_memory_map() {
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// Apply the power-up memory map, i.e. assume that ROM_is_overlay_ = true.
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using Model = Analyser::Static::Macintosh::Target::Model;
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switch(model) {
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default: assert(false);
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case Model::Mac128k:
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case Model::Mac512k:
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case Model::Mac512ke:
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populate_memory_map([] (std::function<void(int target, BusDevice device)> map_to) {
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// Up to $60 0000 mirrors of the ROM alternate with unassigned areas every $10 0000 byes.
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for(int c = 0; c <= 0x600000; c += 0x100000) {
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map_to(c, ((c >> 20)&1) ? BusDevice::ROM : BusDevice::Unassigned);
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}
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map_to(0x800000, BusDevice::RAM);
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map_to(0x900000, BusDevice::Unassigned);
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map_to(0xa00000, BusDevice::SCCReadResetPhase);
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map_to(0xb00000, BusDevice::Unassigned);
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map_to(0xc00000, BusDevice::SCCWrite);
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map_to(0xd00000, BusDevice::Unassigned);
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map_to(0xe00000, BusDevice::IWM);
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map_to(0xe80000, BusDevice::Unassigned);
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map_to(0xf00000, BusDevice::VIA);
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map_to(0xf80000, BusDevice::PhaseRead);
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map_to(0x1000000, BusDevice::Unassigned);
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});
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break;
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// case Model::MacPlus: {
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// int segment = 0;
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// } break;
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}
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}
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void populate_memory_map(std::function<void(std::function<void(int, BusDevice)>)> populator) {
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// Define semantics for below; map_to will write from the current cursor position
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// to the supplied 24-bit address, setting a particular mapped device.
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int segment = 0;
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auto map_to = [&segment, this](int address, BusDevice device) {
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for(; segment < address >> 19; ++segment) {
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this->memory_map_[segment] = device;
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}
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};
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populator(map_to);
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}
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uint32_t ram_mask_ = 0;
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uint32_t rom_mask_ = 0;
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uint16_t rom_[64*1024];
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