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mirror of https://github.com/TomHarte/CLK.git synced 2024-09-29 00:56:21 +00:00

Pull interrupt to start of hsync.

This commit is contained in:
Thomas Harte 2024-09-12 20:45:28 -04:00
parent 60bd877ed9
commit 63d501b629

View File

@ -305,7 +305,7 @@ class CRTCBusHandler {
// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count
// occurs on a leading edge and the mode lock on a trailing.
if(was_hsync_ && !state.hsync) {
if(!was_hsync_ && state.hsync) {
interrupt_timer_.signal_hsync();
}