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Corrects address loading upon accesses of registers other than 0.
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2e379b0834
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@ -415,6 +415,10 @@ void TMS9918::set_register(int address, uint8_t value) {
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return;
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return;
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}
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}
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// The RAM pointer is always set on a second write, regardless of
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// whether the caller is intending to enqueue a VDP operation.
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ram_pointer_ = static_cast<uint16_t>(low_write_ | (value << 8));
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write_phase_ = false;
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write_phase_ = false;
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if(value & 0x80) {
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if(value & 0x80) {
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switch(personality_) {
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switch(personality_) {
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@ -423,7 +427,6 @@ void TMS9918::set_register(int address, uint8_t value) {
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break;
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break;
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case TI::TMS::SMSVDP:
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case TI::TMS::SMSVDP:
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if(value & 0x40) {
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if(value & 0x40) {
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ram_pointer_ = static_cast<uint16_t>(low_write_ | (value << 8));
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master_system_.cram_is_selected = true;
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master_system_.cram_is_selected = true;
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return;
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return;
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}
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}
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@ -507,7 +510,6 @@ void TMS9918::set_register(int address, uint8_t value) {
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}
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}
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} else {
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} else {
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// This is an access via the RAM pointer.
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// This is an access via the RAM pointer.
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ram_pointer_ = static_cast<uint16_t>(low_write_ | (value << 8));
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if(!(value & 0x40)) {
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if(!(value & 0x40)) {
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// A read request is enqueued upon setting the address; conversely a write
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// A read request is enqueued upon setting the address; conversely a write
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// won't be enqueued unless and until some actual data is supplied.
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// won't be enqueued unless and until some actual data is supplied.
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@ -518,8 +520,9 @@ void TMS9918::set_register(int address, uint8_t value) {
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}
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}
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uint8_t TMS9918::get_current_line() {
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uint8_t TMS9918::get_current_line() {
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const int source_row = (column_ < mode_timing_.line_interrupt_position) ? (row_ + mode_timing_.pixel_lines - 1)%mode_timing_.pixel_lines : row_;
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int source_row = (column_ < mode_timing_.line_interrupt_position) ? (row_ + mode_timing_.pixel_lines - 1)%mode_timing_.pixel_lines : row_;
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// This assumes NTSC 192-line. TODO: other modes.
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if(source_row >= 0xdb) source_row -= 5;
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return static_cast<uint8_t>(source_row);
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return static_cast<uint8_t>(source_row);
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}
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}
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