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https://github.com/TomHarte/CLK.git
synced 2024-12-24 12:30:17 +00:00
Added a single IRQ test case, discovering that I'm two cycles short. Whoops!
This commit is contained in:
parent
6e698e908e
commit
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@ -35,7 +35,7 @@
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@ -323,6 +323,7 @@
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@ -397,7 +398,7 @@
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@ -708,6 +709,7 @@
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@ -1253,9 +1255,10 @@
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4B1414631B588A1100E04248 /* Test Binaries */,
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4BC9E1ED1D23449A003FCEE4 /* 6502InterruptTests.swift */,
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);
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path = "Clock SignalTests";
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sourceTree = "<group>";
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@ -1814,7 +1817,8 @@
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4B14145E1B5887AA00E04248 /* CPU6502AllRAM.cpp in Sources */,
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4B14145D1B5887A600E04248 /* CPU6502.cpp in Sources */,
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4B1E85811D176468001EF87D /* 6532Tests.swift in Sources */,
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4B92EACA1B7C112B00246143 /* TimingTests.swift in Sources */,
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4BC9E1EE1D23449A003FCEE4 /* 6502InterruptTests.swift in Sources */,
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4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */,
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4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */,
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4BC751B21D157E61006C31D9 /* 6522Tests.swift in Sources */,
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4B1414621B58888700E04248 /* KlausDormannTests.swift in Sources */,
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48
OSBindings/Mac/Clock SignalTests/6502InterruptTests.swift
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48
OSBindings/Mac/Clock SignalTests/6502InterruptTests.swift
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@ -0,0 +1,48 @@
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//
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// 6502InterruptTests.swift
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// Clock Signal
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//
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// Created by Thomas Harte on 28/06/2016.
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// Copyright © 2016 Thomas Harte. All rights reserved.
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//
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import XCTest
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class MOS6502InterruptTests: XCTestCase {
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var machine: CSTestMachine! = nil
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override func setUp() {
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super.setUp()
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// create a machine full of NOPs
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machine = CSTestMachine()
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for c in 0...65535 {
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machine.setValue(0xea, forAddress: UInt16(c))
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}
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// set the IRQ vector to be 0x1234
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machine.setValue(0x34, forAddress: 0xfffe)
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machine.setValue(0x12, forAddress: 0xffff)
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// add a CLI
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machine.setValue(0x58, forAddress: 0x4000)
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// pick things off at 0x4000
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machine.setValue(0x4000, forRegister: CSTestMachineRegister.ProgramCounter)
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}
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func testIRQLine() {
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// run for four cycles; check that no interrupt has occurred
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machine.runForNumberOfCycles(6)
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XCTAssert(machine.valueForRegister(.ProgramCounter) == 0x4003, "No interrupt should have occurred with line low")
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// enable the interrupt line, check that it was too late
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machine.irqLine = true
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machine.runForNumberOfCycles(2)
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XCTAssert(machine.valueForRegister(.ProgramCounter) == 0x4004, "No interrupt should have occurred from interrupt raised between instructions")
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// run for a further 7 cycles, confirm that the IRQ vector was jumped to
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machine.runForNumberOfCycles(7)
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XCTAssert(machine.valueForRegister(.ProgramCounter) == 0x1234, "Interrupt routine should just have begun")
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}
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}
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@ -9,7 +9,7 @@
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import Foundation
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import XCTest
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class TimingTests: XCTestCase, CSTestMachineJamHandler {
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class MOS6502TimingTests: XCTestCase, CSTestMachineJamHandler {
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private var endTime: UInt32 = 0
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@ -46,12 +46,7 @@ class KlausDormannTests: XCTestCase {
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if newPC == oldPC {
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let error = errorForTrapAddress(oldPC)
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if let error = error {
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NSException(name: "Failed test", reason: error, userInfo: nil).raise()
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} else {
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return
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}
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XCTAssert(error == nil, "Failed with error \(error)")
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}
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}
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}
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@ -41,5 +41,7 @@ extern const uint8_t CSTestMachineJamOpcode;
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@property (nonatomic, readonly) BOOL isJammed;
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@property (nonatomic, readonly) uint32_t timestamp;
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@property (nonatomic, weak) id <CSTestMachineJamHandler> jamHandler;
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@property (nonatomic, assign) BOOL irqLine;
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@property (nonatomic, assign) BOOL nmiLine;
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@end
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@ -99,4 +99,14 @@ class MachineJamHandler: public CPU6502::AllRAMProcessor::JamHandler {
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return _processor.get_timestamp();
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}
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- (void)setIrqLine:(BOOL)irqLine {
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_irqLine = irqLine;
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_processor.set_irq_line(irqLine);
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}
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- (void)setNmiLine:(BOOL)nmiLine {
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_nmiLine = nmiLine;
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_processor.set_nmi_line(nmiLine);
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}
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@end
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@ -493,6 +493,8 @@ template <class T> class Processor {
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*/
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inline const MicroOp *get_irq_program() {
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static const MicroOp reset[] = {
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CycleFetchOperand,
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CycleFetchOperand,
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CyclePushPCH,
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CyclePushPCL,
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OperationSetOperandFromFlags,
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@ -511,6 +513,8 @@ template <class T> class Processor {
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*/
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inline const MicroOp *get_nmi_program() {
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static const MicroOp reset[] = {
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CycleFetchOperand,
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CycleFetchOperand,
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CyclePushPCH,
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CyclePushPCL,
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OperationSetOperandFromFlags,
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