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Implement BTST/etc.

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This commit is contained in:
Thomas Harte 2022-05-04 20:57:22 -04:00
parent 46686b4b9c
commit 64586ca7ba
2 changed files with 29 additions and 52 deletions
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79
InstructionSets/M68k/Implementation/PerformImplementation.hpp
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@ -26,18 +26,6 @@ namespace M68k {
x = ((x & 0xf0f0) >> 4) + (x & 0x0f0f); \ x = ((x & 0xf0f0) >> 4) + (x & 0x0f0f); \
x = ((x & 0xff00) >> 8) + (x & 0x00ff); x = ((x & 0xff00) >> 8) + (x & 0x00ff);
// TODO: decisions outstanding:
//
// (1) should I reintroduce the BTSTl/BTSTw-type distinctions, given that the only way to
// determine them otherwise is by operand types and I'm hoping to treat data into
// here as a black box?
//
// (2) to what extent, if any, should this function have responsibility for a MOVEM, MOVEP,
// etc? This factoring is inteded to separate the bus interface from internal logic so
// is there much to do here in any case? As currently drafted, something else will
// already have had to check the operation and cue up data.
//
template < template <
Model model, Model model,
typename FlowController, typename FlowController,
@ -227,50 +215,37 @@ template <
dest.l -= src.l; dest.l -= src.l;
break; break;
// Two BTSTs: set the zero flag according to the value of the destination masked by // BTST/BCLR/etc: modulo for the mask depends on whether memory or a data register is the target.
// the bit named in the source modulo the operation size. case Operation::BTST: {
// case Operation::BTSTb: const uint32_t mask = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7;
// status.zero_result_ = dest.l & (1 << (src.l & 7)); status.zero_result_ = dest.l & (1 << (src.l & mask));
// break; } break;
//
// case Operation::BTSTl: case Operation::BCLR: {
// zero_result_ = dest.l & (1 << (src.l & 31)); const uint32_t mask = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7;
// break;
// status.zero_result_ = dest.l & (1 << (src.l & mask));
// case Operation::BCLRb: dest.l &= ~(1 << (src.l & mask));
// zero_result_ = dest.l & (1 << (src.l & 7));
// dest.l &= ~(1 << (src.l & 7));
// break;
//
// case Operation::BCLRl:
// zero_result_ = dest.l & (1 << (src.l & 31));
// dest.l &= ~(1 << (src.l & 31));
//
// // Clearing in the top word requires an extra four cycles. // // Clearing in the top word requires an extra four cycles.
// set_next_microcycle_length(HalfCycles(8 + ((src.l & 31) / 16) * 4)); // set_next_microcycle_length(HalfCycles(8 + ((src.l & 31) / 16) * 4));
// break; } break;
//
// case Operation::BCHGl: case Operation::BCHG: {
// zero_result_ = dest.l & (1 << (src.l & 31)); const uint32_t mask = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7;
// dest.l ^= 1 << (src.l & 31);
status.zero_result_ = dest.l & (1 << (src.l & mask));
dest.l ^= 1 << (src.l & mask);
// set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4))); // set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4)));
// break; } break;
//
// case Operation::BCHGb: case Operation::BSET: {
// zero_result_ = dest.b & (1 << (src.l & 7)); const uint32_t mask = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7;
// dest.b ^= 1 << (src.l & 7);
// break; status.zero_result_ = dest.l & (1 << (src.l & mask));
// dest.l |= 1 << (src.l & mask);
// case Operation::BSETl:
// zero_result_ = dest.l & (1 << (src.l & 31));
// dest.l |= 1 << (src.l & 31);
// set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4))); // set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4)));
// break; } break;
//
// case Operation::BSETb:
// zero_result_ = dest.b & (1 << (src.l & 7));
// dest.b |= 1 << (src.l & 7);
// break;
// Bcc: ordinarily evaluates the relevant condition and displacement size and then: // Bcc: ordinarily evaluates the relevant condition and displacement size and then:
// if condition is false, schedules bus operations to get past this instruction; // if condition is false, schedules bus operations to get past this instruction;

2
InstructionSets/M68k/Instruction.hpp
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@ -348,6 +348,8 @@ template <Model model, Operation t_operation = Operation::Undefined> uint8_t ope
case Operation::RORb: case Operation::RORw: case Operation::RORl: case Operation::RORb: case Operation::RORw: case Operation::RORl:
case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl: case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl: case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl:
case Operation::BTST: case Operation::BCHG:
case Operation::BCLR: case Operation::BSET:
return FetchOp1 | FetchOp2 | StoreOp2; return FetchOp1 | FetchOp2 | StoreOp2;
// //