mirror of
https://github.com/TomHarte/CLK.git
synced 2024-06-17 21:30:14 +00:00
Imported what little I have so far in the way of a memory-access cycle complete 6502 and just enough of a pretend Atari 2600 on top to be able to see some playfields in ASCII art.
This commit is contained in:
Thomas Harte
parent
b8947a9aaf
commit
6558ae1425
1
.gitignore
vendored
1
.gitignore
vendored
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@ -16,6 +16,7 @@ DerivedData
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*.hmap
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*.ipa
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*.xcuserstate
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.DS_Store
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# CocoaPods
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#
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152
Machines/Atari2600.cpp
Normal file
152
Machines/Atari2600.cpp
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@ -0,0 +1,152 @@
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//
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// Atari2600.cpp
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// ElectrEm
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//
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// Created by Thomas Harte on 14/07/2015.
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// Copyright © 2015 Thomas Harte. All rights reserved.
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//
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#include "Atari2600.hpp"
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#include <algorithm>
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#include <stdio.h>
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using namespace Atari2600;
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Machine::Machine()
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{
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reset();
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_timestamp = 0;
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_horizontalTimer = 0;
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_pixelPosition = 0;
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}
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void Machine::output_pixels(int count)
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{
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while(count--) {
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int x = _pixelPosition >> 2;
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bool mirrored = (x / 20) && !!(_playFieldControl&1);
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int index = mirrored ? (x%20) : 39 - x;
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int byte = 2 - (index >> 3);
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int bit = (index & 7)^((byte&1) ? 0 : 7);
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_playFieldPixel = (_playField[byte] >> bit)&1;
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// if(!(_pixelPosition&3))
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// fputc(_playFieldPixel && !_vblank ? '*' : ' ', stdout);
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_pixelPosition++;
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}
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}
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void Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t address, uint8_t *value)
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{
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static int lines = 0;
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uint8_t returnValue = 0xff;
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_timestamp++;
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if (_horizontalTimer == 228) {
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_horizontalTimer = 0;
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_pixelPosition = 0;
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// printf("\n");
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lines++;
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}
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if (_horizontalTimer == 69) {
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output_pixels(1);
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}
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if (_horizontalTimer >= 70) {
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output_pixels(3);
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}
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_horizontalTimer += 3;
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// check for a ROM access
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if ((address&0x1000) && isReadOperation(operation)) {
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// if(operation == CPU6502::BusOperation::ReadOpcode) printf("[%04x]\n", address);
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returnValue &= _rom[address&_romMask];
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}
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// check for a RAM access
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if ((address&0x1280) == 0x80) {
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if(isReadOperation(operation)) {
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returnValue &= _ram[address&0x7f];
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} else {
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_ram[address&0x7f] = *value;
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}
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}
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// check for a TIA access
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if (!(address&0x1080)) {
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if(isReadOperation(operation)) {
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} else {
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switch(address & 0x3f) {
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case 0: {
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bool newVsync = !!(*value & 0x02);
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if (newVsync != _vsync) {
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_vsync = newVsync;
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}
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} break;
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case 1: {
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bool newVblank = !!(*value & 0x02);
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if (newVblank != _vblank) {
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_vblank = newVblank;
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}
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} break;
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case 2: {
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int pixelsToRun = 228 - _horizontalTimer;
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_piaTimerValue -= pixelsToRun;
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if (pixelsToRun > 160) pixelsToRun = 160;
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output_pixels(pixelsToRun);
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_horizontalTimer = 228;
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} break;
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case 3: _horizontalTimer = 0; break;
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case 0x0a: _playFieldControl = *value; break;
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case 0x0d: _playField[0] = *value; break;
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case 0x0e: _playField[1] = *value; break;
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case 0x0f: _playField[2] = *value; break;
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}
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}
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// printf("Uncaught TIA %04x\n", address);
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}
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// check for a PIA access
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if ((address&0x1280) == 0x280) {
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if(isReadOperation(operation)) {
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switch(address & 0xf) {
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case 0x04: returnValue &= _piaTimerValue >> _piaTimerShift; break;
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}
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} else {
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switch(address & 0x0f) {
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case 0x04: _piaTimerShift = 0; _piaTimerValue = *value << 0; break;
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case 0x05: _piaTimerShift = 3; _piaTimerValue = *value << 3; break;
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case 0x06: _piaTimerShift = 6; _piaTimerValue = *value << 6; break;
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case 0x07: _piaTimerShift = 10; _piaTimerValue = *value << 10; break;
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}
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}
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// printf("Uncaught PIA %04x\n", address);
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}
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if(isReadOperation(operation)) {
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*value = returnValue;
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}
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_piaTimerValue--;
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}
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void Machine::set_rom(size_t length, const uint8_t *data)
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{
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length = std::min((size_t)4096, length);
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memcpy(_rom, data, length);
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_romMask = length - 1;
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reset();
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}
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46
Machines/Atari2600.hpp
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46
Machines/Atari2600.hpp
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@ -0,0 +1,46 @@
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//
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// Atari2600.hpp
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// ElectrEm
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//
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// Created by Thomas Harte on 14/07/2015.
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// Copyright © 2015 Thomas Harte. All rights reserved.
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//
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#ifndef Atari2600_cpp
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#define Atari2600_cpp
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#include "CPU6502.hpp"
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namespace Atari2600 {
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class Machine: public CPU6502::Processor<Machine> {
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public:
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Machine();
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void perform_bus_operation(CPU6502::BusOperation operation, uint16_t address, uint8_t *value);
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void set_rom(size_t length, const uint8_t *data);
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private:
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uint8_t _rom[4096], _ram[128];
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uint16_t _romMask;
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uint8_t _playField[3], _playFieldControl;
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uint64_t _timestamp;
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bool _vsync, _vblank;
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unsigned int _piaTimerValue;
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unsigned int _piaTimerShift;
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int _horizontalTimer;
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int _pixelPosition;
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uint8_t _playFieldPixel;
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void output_pixels(int count);
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};
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}
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#endif /* Atari2600_cpp */
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11
Processors/6502/CPU6502.cpp
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11
Processors/6502/CPU6502.cpp
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//
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// CPU6502.cpp
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// ElectrEm
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//
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// Created by Thomas Harte on 09/07/2015.
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// Copyright © 2015 Thomas Harte. All rights reserved.
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//
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#include "CPU6502.hpp"
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const uint8_t CPU6502::JamOpcode = 0xf2;
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908
Processors/6502/CPU6502.hpp
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908
Processors/6502/CPU6502.hpp
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@ -0,0 +1,908 @@
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//
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// CPU6502.hpp
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// ElectrEm
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//
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// Created by Thomas Harte on 09/07/2015.
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// Copyright © 2015 Thomas Harte. All rights reserved.
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//
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#ifndef CPU6502_cpp
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#define CPU6502_cpp
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#include <stdio.h>
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#include <stdint.h>
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namespace CPU6502 {
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enum class Register {
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LastOperationAddress,
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ProgramCounter,
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StackPointer,
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Flags,
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A,
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S
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};
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enum Flag {
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Sign = 0x80,
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Overflow = 0x40,
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Always = 0x20,
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Break = 0x10,
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Decimal = 0x08,
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Interrupt = 0x04,
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Zero = 0x02,
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Carry = 0x01
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};
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enum BusOperation {
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Read, ReadOpcode, Write, None
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};
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#define isReadOperation(v) (v != CPU6502::BusOperation::Write)
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extern const uint8_t JamOpcode;
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template <class T> class Processor {
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public:
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class JamHandler {
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public:
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virtual void processor_did_jam(Processor *processor, uint16_t address) = 0;
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};
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private:
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enum MicroOp {
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CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
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CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
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CycleSetIReadBRKLow, CycleReadBRKHigh, CycleReadFromS, CycleReadFromPC,
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CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA,
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CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
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CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute,
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OperationLoadAddressZeroPage, CycleLoadAddessZeroX, CycleLoadAddessZeroY, CycleAddXToAddressLow,
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CycleAddYToAddressLow, CycleCorrectAddressHigh, OperationMoveToNextProgram, OperationIncrementPC,
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CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA,
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CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand,
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OperationIncrementOperand, OperationORA, OperationAND, OperationEOR,
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OperationINS, OperationADC, OperationSBC, OperationLDA,
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OperationLDX, OperationLDY, OperationLAX, OperationSTA,
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OperationSTX, OperationSTY, OperationSAX, OperationSHA,
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OperationSHX, OperationSHY, OperationSHS, OperationCMP,
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OperationCPX, OperationCPY, OperationBIT, OperationASL,
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OperationASO, OperationROL, OperationRLA, OperationLSR,
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OperationLSE, OperationASR, OperationROR, OperationRRA,
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OperationCLC, OperationCLI, OperationCLV, OperationCLD,
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OperationSEC, OperationSEI, OperationSED, OperationINC,
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OperationDEC, OperationINX, OperationDEX, OperationINY,
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OperationDEY, OperationBPL, OperationBMI, OperationBVC,
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OperationBVS, OperationBCC, OperationBCS, OperationBNE,
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OperationBEQ, OperationTXA, OperationTYA, OperationTXS,
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OperationTAY, OperationTAX, OperationTSX, OperationARR,
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OperationSBX, OperationLXA, OperationANE, OperationANC,
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OperationLAS, CycleAddSignedOperandToPC, OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet,
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OperationSetFlagsFromA, CycleScheduleJam
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};
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#define JAM {CycleFetchOperand, CycleScheduleJam, OperationMoveToNextProgram}
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union RegisterPair {
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uint16_t full;
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struct {
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uint8_t low, high;
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} bytes;
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};
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RegisterPair _pc, _lastOperationPC;
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uint8_t _a, _x, _y, _s;
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uint8_t _carryFlag, _negativeResult, _zeroResult, _decimalFlag, _overflowFlag, _interruptFlag;
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uint8_t _operation, _operand;
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RegisterPair _address, _nextAddress;
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const MicroOp *_scheduledPrograms[4];
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unsigned int _scheduleProgramsWritePointer, _scheduleProgramsReadPointer, _scheduleProgramProgramCounter;
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BusOperation _nextBusOperation;
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uint16_t _busAddress;
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uint8_t *_busValue;
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uint64_t _externalBus;
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void schedule_program(const MicroOp *program)
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{
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_scheduledPrograms[_scheduleProgramsWritePointer] = program;
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_scheduleProgramsWritePointer = (_scheduleProgramsWritePointer+1)&3;
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}
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uint8_t get_flags()
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{
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return _carryFlag | _overflowFlag | _interruptFlag | (_negativeResult & 0x80) | (_zeroResult ? 0 : Flag::Zero) | Flag::Always | _decimalFlag;
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}
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void set_flags(uint8_t flags)
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{
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_carryFlag = flags & Flag::Carry;
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_negativeResult = flags & Flag::Sign;
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_zeroResult = (~flags) & Flag::Zero;
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_overflowFlag = flags & Flag::Overflow;
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_interruptFlag = flags & Flag::Interrupt;
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_decimalFlag = flags & Flag::Decimal;
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}
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void decode_operation(uint8_t operation)
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{
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#define Program(...) {__VA_ARGS__, OperationMoveToNextProgram}
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#define Absolute CycleLoadAddressAbsolute
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#define AbsoluteX CycleLoadAddressAbsolute, CycleAddXToAddressLow, CycleCorrectAddressHigh
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#define AbsoluteY CycleLoadAddressAbsolute, CycleAddYToAddressLow, CycleCorrectAddressHigh
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#define Zero OperationLoadAddressZeroPage
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#define ZeroX CycleLoadAddessZeroX
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#define ZeroY CycleLoadAddessZeroY
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#define IndexedIndirect CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh
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#define IndirectIndexed CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLow, CycleCorrectAddressHigh
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#define Read(op) CycleFetchOperandFromAddress, op
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#define Write(op) op, CycleWriteOperandToAddress
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#define ReadModifyWrite(...) CycleFetchOperandFromAddress, __VA_ARGS__, CycleWriteOperandToAddress
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#define AbsoluteRead(op) Program(Absolute, Read(op))
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#define AbsoluteXRead(op) Program(AbsoluteX, Read(op))
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#define AbsoluteYRead(op) Program(AbsoluteY, Read(op))
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#define ZeroRead(op) Program(Zero, Read(op))
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#define ZeroXRead(op) Program(ZeroX, Read(op))
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#define ZeroYRead(op) Program(ZeroY, Read(op))
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#define IndexedIndirectRead(op) Program(IndexedIndirect, Read(op))
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#define IndirectIndexedRead(op) Program(IndirectIndexed, Read(op))
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#define AbsoluteWrite(op) Program(Absolute, Write(op))
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#define AbsoluteXWrite(op) Program(AbsoluteX, Write(op))
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#define AbsoluteYWrite(op) Program(AbsoluteY, Write(op))
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#define ZeroWrite(op) Program(Zero, Write(op))
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#define ZeroXWrite(op) Program(ZeroX, Write(op))
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#define ZeroYWrite(op) Program(ZeroY, Write(op))
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#define IndexedIndirectWrite(op) Program(IndexedIndirect, Write(op))
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#define IndirectIndexedWrite(op) Program(IndirectIndexed, Write(op))
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#define AbsoluteReadModifyWrite(...) Program(Absolute, ReadModifyWrite(__VA_ARGS__))
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#define AbsoluteXReadModifyWrite(...) Program(AbsoluteX, ReadModifyWrite(__VA_ARGS__))
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#define AbsoluteYReadModifyWrite(...) Program(AbsoluteY, ReadModifyWrite(__VA_ARGS__))
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#define ZeroReadModifyWrite(...) Program(Zero, ReadModifyWrite(__VA_ARGS__))
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#define ZeroXReadModifyWrite(...) Program(ZeroX, ReadModifyWrite(__VA_ARGS__))
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#define ZeroYReadModifyWrite(...) Program(ZeroY, ReadModifyWrite(__VA_ARGS__))
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#define IndexedIndirectReadModifyWrite(...) Program(IndexedIndirect, ReadModifyWrite(__VA_ARGS__))
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#define IndirectIndexedReadModifyWrite(...) Program(IndirectIndexed, ReadModifyWrite(__VA_ARGS__))
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#define Immediate(op) Program(OperationIncrementPC, op)
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#define Implied(op) Program(OperationCopyOperandFromA, op, OperationCopyOperandToA)
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#define ZeroNop() Program(Zero)
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#define ZeroXNop() Program(ZeroX)
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#define AbsoluteNop() Program(Absolute)
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#define AbsoluteXNop() Program(AbsoluteX)
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#define ImpliedNop() {OperationMoveToNextProgram}
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#define ImmediateNop() Program(OperationIncrementPC)
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static const MicroOp operations[256][9] = {
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/* 0x00 BRK */ Program(CycleIncPCPushPCH, CyclePushPCL, OperationSetOperandFromFlagsWithBRKSet, CyclePushOperand, CycleSetIReadBRKLow, CycleReadBRKHigh),
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/* 0x01 ORA x, ind */ IndexedIndirectRead(OperationORA),
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/* 0x02 JAM */ JAM, /* 0x03 ASO x, ind */ IndexedIndirectReadModifyWrite(OperationASO),
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/* 0x04 NOP zpg */ ZeroNop(), /* 0x05 ORA zpg */ ZeroRead(OperationORA),
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/* 0x06 ASL zpg */ ZeroReadModifyWrite(OperationASL), /* 0x07 ASO zpg */ ZeroReadModifyWrite(OperationASO),
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/* 0x08 PHP */ Program(OperationSetOperandFromFlagsWithBRKSet, CyclePushOperand),
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/* 0x09 ORA # */ Immediate(OperationORA),
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/* 0x0a ASL A */ Implied(OperationASL), /* 0x0b ANC # */ Immediate(OperationANC),
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/* 0x0c NOP abs */ AbsoluteNop(), /* 0x0d ORA abs */ AbsoluteRead(OperationORA),
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/* 0x0e ASL abs */ AbsoluteReadModifyWrite(OperationASL), /* 0x0f ASO abs */ AbsoluteReadModifyWrite(OperationASO),
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/* 0x10 BPL */ Program(OperationBPL), /* 0x11 ORA ind, y */ IndirectIndexedRead(OperationORA),
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/* 0x12 JAM */ JAM, /* 0x13 ASO ind, y */ IndirectIndexedReadModifyWrite(OperationASO),
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/* 0x14 NOP zpg, x */ ZeroXNop(), /* 0x15 ORA zpg, x */ ZeroXRead(OperationORA),
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/* 0x16 ASL zpg, x */ ZeroXReadModifyWrite(OperationASL), /* 0x17 ASO zpg, x */ ZeroXReadModifyWrite(OperationASO),
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/* 0x18 CLC */ Program(OperationCLC), /* 0x19 ORA abs, y */ AbsoluteYRead(OperationORA),
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/* 0x1a NOP # */ ImpliedNop(), /* 0x1b ASO abs, y */ AbsoluteYReadModifyWrite(OperationASO),
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/* 0x1c NOP abs, x */ AbsoluteXNop(), /* 0x1d ORA abs, x */ AbsoluteXRead(OperationORA),
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/* 0x1e ASL abs, x */ AbsoluteXReadModifyWrite(OperationASL), /* 0x1f ASO abs, x */ AbsoluteXReadModifyWrite(OperationASO),
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/* 0x20 JSR abs */ Program(CycleIncrementPCAndReadStack, CyclePushPCH, CyclePushPCL, CycleReadPCHLoadPCL),
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/* 0x21 AND x, ind */ IndexedIndirectRead(OperationAND),
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/* 0x22 JAM */ JAM, /* 0x23 RLA x, ind */ IndexedIndirectReadModifyWrite(OperationRLA),
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/* 0x24 BIT zpg */ ZeroRead(OperationBIT), /* 0x25 AND zpg */ ZeroRead(OperationAND),
|
||||
/* 0x26 ROL zpg */ ZeroReadModifyWrite(OperationROL), /* 0x27 RLA zpg */ ZeroReadModifyWrite(OperationRLA),
|
||||
/* 0x28 PLP */ Program(CycleReadFromS, CyclePullOperand, OperationSetFlagsFromOperand),
|
||||
/* 0x29 AND A # */ Immediate(OperationAND),
|
||||
/* 0x2a ROL A */ Implied(OperationROL), /* 0x2b ANC # */ Immediate(OperationANC),
|
||||
/* 0x2c BIT abs */ AbsoluteRead(OperationBIT), /* 0x2d AND abs */ AbsoluteRead(OperationAND),
|
||||
/* 0x2e ROL abs */ AbsoluteReadModifyWrite(OperationROL), /* 0x2f RLA abs */ AbsoluteReadModifyWrite(OperationRLA),
|
||||
/* 0x30 BMI */ Program(OperationBMI), /* 0x31 AND ind, y */ IndirectIndexedRead(OperationAND),
|
||||
/* 0x32 JAM */ JAM, /* 0x33 RLA ind, y */ IndirectIndexedReadModifyWrite(OperationRLA),
|
||||
/* 0x34 NOP zpg, x */ ZeroXNop(), /* 0x35 AND zpg, x */ ZeroXRead(OperationAND),
|
||||
/* 0x36 ROL zpg, x */ ZeroXReadModifyWrite(OperationROL), /* 0x37 RLA zpg, x */ ZeroXReadModifyWrite(OperationRLA),
|
||||
/* 0x38 SEC */ Program(OperationSEC), /* 0x39 AND abs, y */ AbsoluteYRead(OperationAND),
|
||||
/* 0x3a NOP # */ ImpliedNop(), /* 0x3b RLA abs, y */ AbsoluteYReadModifyWrite(OperationRLA),
|
||||
/* 0x3c NOP abs, x */ AbsoluteXNop(), /* 0x3d AND abs, x */ AbsoluteXRead(OperationAND),
|
||||
/* 0x3e ROL abs, x */ AbsoluteXReadModifyWrite(OperationROL), /* 0x3f RLA abs, x */ AbsoluteXReadModifyWrite(OperationRLA),
|
||||
/* 0x40 RTI */ Program(CycleReadFromS, CyclePullOperand, OperationSetFlagsFromOperand, CyclePullPCL, CyclePullPCH),
|
||||
/* 0x41 EOR x, ind */ IndexedIndirectRead(OperationEOR),
|
||||
/* 0x42 JAM */ JAM, /* 0x43 LSE x, ind */ IndexedIndirectReadModifyWrite(OperationLSE),
|
||||
/* 0x44 NOP zpg */ ZeroNop(), /* 0x45 EOR zpg */ ZeroRead(OperationEOR),
|
||||
/* 0x46 LSR zpg */ ZeroReadModifyWrite(OperationLSR), /* 0x47 LSE zpg */ ZeroReadModifyWrite(OperationLSE),
|
||||
/* 0x48 PHA */ Program(CyclePushA), /* 0x49 EOR # */ Immediate(OperationEOR),
|
||||
/* 0x4a LSR A */ Implied(OperationLSR), /* 0x4b ASR A */ Immediate(OperationASR),
|
||||
/* 0x4c JMP abs */ Program(CycleIncrementPCReadPCHLoadPCL), /* 0x4d EOR abs */ AbsoluteRead(OperationEOR),
|
||||
/* 0x4e LSR abs */ AbsoluteReadModifyWrite(OperationLSR), /* 0x4f LSE abs */ AbsoluteReadModifyWrite(OperationLSE),
|
||||
/* 0x50 BVC */ Program(OperationBVC), /* 0x51 EOR ind, y */ IndirectIndexedRead(OperationEOR),
|
||||
/* 0x52 JAM */ JAM, /* 0x53 LSE ind, y */ IndirectIndexedReadModifyWrite(OperationLSE),
|
||||
/* 0x54 NOP zpg, x */ ZeroXNop(), /* 0x55 EOR zpg, x */ ZeroXRead(OperationEOR),
|
||||
/* 0x56 LSR zpg, x */ ZeroXReadModifyWrite(OperationLSR), /* 0x57 LSE zpg, x */ ZeroXReadModifyWrite(OperationLSE),
|
||||
/* 0x58 CLI */ Program(OperationCLI), /* 0x59 EOR abs, y */ AbsoluteYRead(OperationEOR),
|
||||
/* 0x5a NOP # */ ImpliedNop(), /* 0x5b LSE abs, y */ AbsoluteYReadModifyWrite(OperationLSE),
|
||||
/* 0x5c NOP abs, x */ AbsoluteXNop(), /* 0x5d EOR abs, x */ AbsoluteXRead(OperationEOR),
|
||||
/* 0x5e LSR abs, x */ AbsoluteXReadModifyWrite(OperationLSR), /* 0x5f LSE abs, x */ AbsoluteXReadModifyWrite(OperationLSE),
|
||||
/* 0x60 RTS */ Program(CycleReadFromS, CyclePullPCL, CyclePullPCH, CycleReadAndIncrementPC),
|
||||
/* 0x61 ADC x, ind */ IndexedIndirectRead(OperationADC),
|
||||
/* 0x62 JAM */ JAM, /* 0x63 RRA x, ind */ IndexedIndirectReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x64 NOP zpg */ ZeroNop(), /* 0x65 ADC zpg */ ZeroRead(OperationADC),
|
||||
/* 0x66 ROR zpg */ ZeroReadModifyWrite(OperationROR), /* 0x67 RRA zpg */ ZeroReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x68 PLA */ Program(CycleReadFromS, CyclePullA, OperationSetFlagsFromA), /* 0x69 ADC # */ Immediate(OperationADC),
|
||||
/* 0x6a ROR A */ Implied(OperationROR), /* 0x6b ARR # */ Immediate(OperationARR),
|
||||
/* 0x6c JMP (abs) */ Program(CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress),
|
||||
/* 0x6d ADC abs */ AbsoluteRead(OperationADC),
|
||||
/* 0x6e ROR abs */ AbsoluteReadModifyWrite(OperationROR), /* 0x6f RRA abs */ AbsoluteReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x70 BVS */ Program(OperationBVS), /* 0x71 ADC ind, y */ IndirectIndexedRead(OperationADC),
|
||||
/* 0x72 JAM */ JAM, /* 0x73 RRA ind, y */ IndirectIndexedReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x74 NOP zpg, x */ ZeroXNop(), /* 0x75 ADC zpg, x */ ZeroXRead(OperationADC),
|
||||
/* 0x76 ROR zpg, x */ ZeroXReadModifyWrite(OperationROR), /* 0x77 RRA zpg, x */ ZeroXReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x78 SEI */ Program(OperationSEI), /* 0x79 ADC abs, y */ AbsoluteYRead(OperationADC),
|
||||
/* 0x7a NOP # */ ImpliedNop(), /* 0x7b RRA abs, y */ AbsoluteYReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x7c NOP abs, x */ AbsoluteXNop(), /* 0x7d ADC abs, x */ AbsoluteXRead(OperationADC),
|
||||
/* 0x7e ROR abs, x */ AbsoluteXReadModifyWrite(OperationROR), /* 0x7f RRA abs, x */ AbsoluteXReadModifyWrite(OperationRRA, OperationADC),
|
||||
/* 0x80 NOP # */ ImmediateNop(), /* 0x81 STA x, ind */ IndexedIndirectWrite(OperationSTA),
|
||||
/* 0x82 NOP # */ ImmediateNop(), /* 0x83 SAX x, ind */ IndexedIndirectWrite(OperationSAX),
|
||||
/* 0x84 STY zpg */ ZeroWrite(OperationSTY), /* 0x85 STA zpg */ ZeroWrite(OperationSTA),
|
||||
/* 0x86 STX zpg */ ZeroWrite(OperationSTX), /* 0x87 SAX zpg */ ZeroWrite(OperationSAX),
|
||||
/* 0x88 DEY */ Program(OperationDEY), /* 0x89 NOP # */ ImmediateNop(),
|
||||
/* 0x8a TXA */ Program(OperationTXA), /* 0x8b ANE # */ Immediate(OperationANE),
|
||||
/* 0x8c STY abs */ AbsoluteWrite(OperationSTY), /* 0x8d STA abs */ AbsoluteWrite(OperationSTA),
|
||||
/* 0x8e STX abs */ AbsoluteWrite(OperationSTX), /* 0x8f SAX abs */ AbsoluteWrite(OperationSAX),
|
||||
/* 0x90 BCC */ Program(OperationBCC), /* 0x91 STA ind, y */ IndirectIndexedWrite(OperationSTA),
|
||||
/* 0x92 JAM */ JAM, /* 0x93 SHA ind, y */ IndirectIndexedWrite(OperationSHA),
|
||||
/* 0x94 STY zpg, x */ ZeroXWrite(OperationSTY), /* 0x95 STA zpg, x */ ZeroXWrite(OperationSTA),
|
||||
/* 0x96 STX zpg, y */ ZeroYWrite(OperationSTX), /* 0x97 SAX zpg, y */ ZeroYWrite(OperationSAX),
|
||||
/* 0x98 TYA */ Program(OperationTYA), /* 0x99 STA abs, y */ AbsoluteYWrite(OperationSTA),
|
||||
/* 0x9a TXS */ Program(OperationTXS), /* 0x9b SHS abs, y */ AbsoluteYWrite(OperationSHS),
|
||||
/* 0x9c SHY abs, x */ AbsoluteXWrite(OperationSHY), /* 0x9d STA abs, x */ AbsoluteXWrite(OperationSTA),
|
||||
/* 0x9e SHX abs, y */ AbsoluteYWrite(OperationSHX), /* 0x9f SHA abs, y */ AbsoluteYWrite(OperationSHA),
|
||||
/* 0xa0 LDY # */ Immediate(OperationLDY), /* 0xa1 LDA x, ind */ IndexedIndirectRead(OperationLDA),
|
||||
/* 0xa2 LDX # */ Immediate(OperationLDX), /* 0xa3 LAX x, ind */ IndexedIndirectRead(OperationLAX),
|
||||
/* 0xa4 LDY zpg */ ZeroRead(OperationLDY), /* 0xa5 LDA zpg */ ZeroRead(OperationLDA),
|
||||
/* 0xa6 LDX zpg */ ZeroRead(OperationLDX), /* 0xa7 LAX zpg */ ZeroRead(OperationLAX),
|
||||
/* 0xa8 TAY */ Program(OperationTAY), /* 0xa9 LDA # */ Immediate(OperationLDA),
|
||||
/* 0xaa TAX */ Program(OperationTAX), /* 0xab LXA # */ Immediate(OperationLXA),
|
||||
/* 0xac LDY abs */ AbsoluteRead(OperationLDY), /* 0xad LDA abs */ AbsoluteRead(OperationLDA),
|
||||
/* 0xae LDX abs */ AbsoluteRead(OperationLDX), /* 0xaf LAX abs */ AbsoluteRead(OperationLAX),
|
||||
/* 0xb0 BCS */ Program(OperationBCS), /* 0xb1 LDA ind, y */ IndirectIndexedRead(OperationLDA),
|
||||
/* 0xb2 JAM */ JAM, /* 0xb3 LAX ind, y */ IndirectIndexedRead(OperationLAX),
|
||||
/* 0xb4 LDY zpg, x */ ZeroXRead(OperationLDY), /* 0xb5 LDA zpg, x */ ZeroXRead(OperationLDA),
|
||||
/* 0xb6 LDX zpg, y */ ZeroYRead(OperationLDX), /* 0xb7 LAX zpg, x */ ZeroYRead(OperationLAX),
|
||||
/* 0xb8 CLV */ Program(OperationCLV), /* 0xb9 LDA abs, y */ AbsoluteYRead(OperationLDA),
|
||||
/* 0xba TSX */ Program(OperationTSX), /* 0xbb LAS abs, y */ AbsoluteYRead(OperationLAS),
|
||||
/* 0xbc LDY abs, x */ AbsoluteXRead(OperationLDY), /* 0xbd LDA abs, x */ AbsoluteXRead(OperationLDA),
|
||||
/* 0xbe LDX abs, y */ AbsoluteYRead(OperationLDX), /* 0xbf LAX abs, y */ AbsoluteYRead(OperationLAX),
|
||||
/* 0xc0 CPY # */ Immediate(OperationCPY), /* 0xc1 CMP x, ind */ IndexedIndirectRead(OperationCMP),
|
||||
/* 0xc2 NOP # */ ImmediateNop(), /* 0xc3 DCP x, ind */ IndexedIndirectReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xc4 CPY zpg */ ZeroRead(OperationCPY), /* 0xc5 CMP zpg */ ZeroRead(OperationCMP),
|
||||
/* 0xc6 DEC zpg */ ZeroReadModifyWrite(OperationDEC), /* 0xc7 DCP zpg */ ZeroReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xc8 INY */ Program(OperationINY), /* 0xc9 CMP # */ Immediate(OperationCMP),
|
||||
/* 0xca DEX */ Program(OperationDEX), /* 0xcb ARR # */ Immediate(OperationSBX),
|
||||
/* 0xcc CPY abs */ AbsoluteRead(OperationCPY), /* 0xcd CMP abs */ AbsoluteRead(OperationCMP),
|
||||
/* 0xce DEC abs */ AbsoluteReadModifyWrite(OperationDEC), /* 0xcf DCP abs */ AbsoluteReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xd0 BNE */ Program(OperationBNE), /* 0xd1 CMP ind, y */ IndirectIndexedRead(OperationCMP),
|
||||
/* 0xd2 JAM */ JAM, /* 0xd3 DCP ind, y */ IndirectIndexedReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xd4 NOP zpg, x */ ZeroXNop(), /* 0xd5 CMP zpg, x */ ZeroXRead(OperationCMP),
|
||||
/* 0xd6 DEC zpg, x */ ZeroXReadModifyWrite(OperationDEC), /* 0xd7 DCP zpg, x */ ZeroXReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xd8 CLD */ Program(OperationCLD), /* 0xd9 CMP abs, y */ AbsoluteYRead(OperationCMP),
|
||||
/* 0xda NOP # */ ImpliedNop(), /* 0xdb DCP abs, y */ AbsoluteYReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xdc NOP abs, x */ AbsoluteXNop(), /* 0xdd CMP abs, x */ AbsoluteXRead(OperationCMP),
|
||||
/* 0xde DEC abs, x */ AbsoluteXReadModifyWrite(OperationDEC), /* 0xdf DCP abs, x */ AbsoluteXReadModifyWrite(OperationDecrementOperand, OperationCMP),
|
||||
/* 0xe0 CPX # */ Immediate(OperationCPX), /* 0xe1 SBC x, ind */ IndexedIndirectRead(OperationSBC),
|
||||
/* 0xe2 NOP # */ ImmediateNop(), /* 0xe3 INS x, ind */ IndexedIndirectReadModifyWrite(OperationINS),
|
||||
/* 0xe4 CPX zpg */ ZeroRead(OperationCPX), /* 0xe5 SBC zpg */ ZeroRead(OperationSBC),
|
||||
/* 0xe6 INC zpg */ ZeroReadModifyWrite(OperationINC), /* 0xe7 INS zpg */ ZeroReadModifyWrite(OperationINS),
|
||||
/* 0xe8 INX */ Program(OperationINX), /* 0xe9 SBC # */ Immediate(OperationSBC),
|
||||
/* 0xea NOP # */ ImpliedNop(), /* 0xeb SBC # */ Immediate(OperationSBC),
|
||||
/* 0xec CPX abs */ AbsoluteRead(OperationCPX), /* 0xed SBC abs */ AbsoluteRead(OperationSBC),
|
||||
/* 0xee INC abs */ AbsoluteReadModifyWrite(OperationINC), /* 0xef INS abs */ AbsoluteReadModifyWrite(OperationINS),
|
||||
/* 0xf0 BEQ */ Program(OperationBEQ), /* 0xf1 SBC ind, y */ IndirectIndexedRead(OperationSBC),
|
||||
/* 0xf2 JAM */ JAM, /* 0xf3 INS ind, y */ IndirectIndexedReadModifyWrite(OperationINS),
|
||||
/* 0xf4 NOP zpg, x */ ZeroXNop(), /* 0xf5 SBC zpg, x */ ZeroXRead(OperationSBC),
|
||||
/* 0xf6 INC zpg, x */ ZeroXReadModifyWrite(OperationINC), /* 0xf7 INS zpg, x */ ZeroXReadModifyWrite(OperationINS),
|
||||
/* 0xf8 SED */ Program(OperationSED), /* 0xf9 SBC abs, y */ AbsoluteYRead(OperationSBC),
|
||||
/* 0xfa NOP # */ ImpliedNop(), /* 0xfb INS abs, y */ AbsoluteYReadModifyWrite(OperationINS),
|
||||
/* 0xfc NOP abs, x */ AbsoluteXNop(), /* 0xfd SBC abs, x */ AbsoluteXRead(OperationSBC),
|
||||
/* 0xfe INC abs, x */ AbsoluteXReadModifyWrite(OperationINC), /* 0xff INS abs, x */ AbsoluteXReadModifyWrite(OperationINS),
|
||||
};
|
||||
|
||||
#undef Program
|
||||
#undef Absolute
|
||||
#undef AbsoluteX
|
||||
#undef AbsoluteY
|
||||
#undef Zero
|
||||
#undef ZeroX
|
||||
#undef ZeroY
|
||||
#undef IndexedIndirect
|
||||
#undef IndirectIndexed
|
||||
#undef Read
|
||||
#undef Write
|
||||
#undef ReadModifyWrite
|
||||
#undef AbsoluteRead
|
||||
#undef AbsoluteXRead
|
||||
#undef AbsoluteYRead
|
||||
#undef ZeroRead
|
||||
#undef ZeroXRead
|
||||
#undef ZeroYRead
|
||||
#undef IndexedIndirectRead
|
||||
#undef IndirectIndexedRead
|
||||
#undef AbsoluteWrite
|
||||
#undef AbsoluteXWrite
|
||||
#undef AbsoluteYWrite
|
||||
#undef ZeroWrite
|
||||
#undef ZeroXWrite
|
||||
#undef ZeroYWrite
|
||||
#undef IndexedIndirectWrite
|
||||
#undef IndirectIndexedWrite
|
||||
#undef AbsoluteReadModifyWrite
|
||||
#undef AbsoluteXReadModifyWrite
|
||||
#undef AbsoluteYReadModifyWrite
|
||||
#undef ZeroReadModifyWrite
|
||||
#undef ZeroXReadModifyWrite
|
||||
#undef ZeroYReadModify
|
||||
#undef IndexedIndirectReadModify
|
||||
#undef IndirectIndexedReadModify
|
||||
#undef Immediate
|
||||
#undef Implied
|
||||
|
||||
schedule_program(operations[operation]);
|
||||
}
|
||||
|
||||
bool _is_jammed;
|
||||
JamHandler *_jam_handler;
|
||||
|
||||
|
||||
public:
|
||||
Processor()
|
||||
{
|
||||
_scheduleProgramsWritePointer = _scheduleProgramsReadPointer = 0;
|
||||
_scheduledPrograms[0] = _scheduledPrograms[1] = _scheduledPrograms[2] = _scheduledPrograms[3] = nullptr;
|
||||
_is_jammed = false;
|
||||
_jam_handler = nullptr;
|
||||
}
|
||||
|
||||
void run_for_cycles(int number_of_cycles)
|
||||
{
|
||||
static const MicroOp doBranch[] = {
|
||||
CycleReadFromPC,
|
||||
CycleAddSignedOperandToPC,
|
||||
OperationMoveToNextProgram
|
||||
};
|
||||
static uint8_t throwaway_target;
|
||||
static const MicroOp fetch_decode_execute[] =
|
||||
{
|
||||
CycleFetchOperation,
|
||||
CycleFetchOperand,
|
||||
OperationDecodeOperation,
|
||||
OperationMoveToNextProgram
|
||||
};
|
||||
|
||||
#define checkSchedule(op) \
|
||||
if(!_scheduledPrograms[_scheduleProgramsReadPointer]) {\
|
||||
_scheduleProgramsReadPointer = _scheduleProgramsWritePointer = _scheduleProgramProgramCounter = 0;\
|
||||
schedule_program(fetch_decode_execute);\
|
||||
op;\
|
||||
}
|
||||
|
||||
checkSchedule();
|
||||
|
||||
while(number_of_cycles) {
|
||||
|
||||
const MicroOp cycle = _scheduledPrograms[_scheduleProgramsReadPointer][_scheduleProgramProgramCounter];
|
||||
_scheduleProgramProgramCounter++;
|
||||
|
||||
#define read_op(val, addr) _nextBusOperation = BusOperation::ReadOpcode; _busAddress = addr; _busValue = &val
|
||||
#define read_mem(val, addr) _nextBusOperation = BusOperation::Read; _busAddress = addr; _busValue = &val
|
||||
#define throwaway_read(addr) _nextBusOperation = BusOperation::Read; _busAddress = addr; _busValue = &throwaway_target
|
||||
#define write_mem(val, addr) _nextBusOperation = BusOperation::Write; _busAddress = addr; _busValue = &val
|
||||
|
||||
switch(cycle) {
|
||||
|
||||
#pragma mark - Fetch/Decode
|
||||
|
||||
case CycleFetchOperation:
|
||||
_lastOperationPC = _pc;
|
||||
_pc.full++;
|
||||
read_op(_operation, _lastOperationPC.full);
|
||||
break;
|
||||
|
||||
case CycleFetchOperand:
|
||||
read_mem(_operand, _pc.full);
|
||||
break;
|
||||
|
||||
case OperationDecodeOperation:
|
||||
decode_operation(_operation);
|
||||
break;
|
||||
|
||||
case OperationMoveToNextProgram:
|
||||
_scheduledPrograms[_scheduleProgramsReadPointer] = NULL;
|
||||
_scheduleProgramsReadPointer = (_scheduleProgramsReadPointer+1)&3;
|
||||
_scheduleProgramProgramCounter = 0;
|
||||
checkSchedule();
|
||||
break;
|
||||
|
||||
#define push(v) \
|
||||
{\
|
||||
uint16_t targetAddress = _s | 0x100; _s--;\
|
||||
write_mem(v, targetAddress);\
|
||||
}
|
||||
|
||||
case CycleIncPCPushPCH: _pc.full++; // deliberate fallthrough
|
||||
case CyclePushPCH: push(_pc.bytes.high); break;
|
||||
case CyclePushPCL: push(_pc.bytes.low); break;
|
||||
case CyclePushOperand: push(_operand); break;
|
||||
case CyclePushA: push(_a); break;
|
||||
|
||||
#undef push
|
||||
|
||||
case CycleReadFromS: throwaway_read(_s | 0x100); break;
|
||||
case CycleReadFromPC: throwaway_read(_pc.full); break;
|
||||
|
||||
case CycleSetIReadBRKLow: _interruptFlag = Flag::Interrupt; read_mem(_pc.bytes.low, 0xfffe); break;
|
||||
case CycleReadBRKHigh: read_mem(_pc.bytes.high, 0xffff); break;
|
||||
|
||||
case CyclePullPCL: _s++; read_mem(_pc.bytes.low, _s | 0x100); break;
|
||||
case CyclePullPCH: _s++; read_mem(_pc.bytes.high, _s | 0x100); break;
|
||||
case CyclePullA: _s++; read_mem(_a, _s | 0x100); break;
|
||||
case CyclePullOperand: _s++; read_mem(_operand, _s | 0x100); break;
|
||||
case OperationSetFlagsFromOperand: set_flags(_operand); break;
|
||||
case OperationSetOperandFromFlagsWithBRKSet: _operand = get_flags() | Flag::Break; break;
|
||||
case OperationSetFlagsFromA: _zeroResult = _negativeResult = _a; break;
|
||||
|
||||
case CycleIncrementPCAndReadStack: _pc.full++; throwaway_read(_s | 0x100); break;
|
||||
case CycleReadPCLFromAddress: read_mem(_pc.bytes.low, _address.full); break;
|
||||
case CycleReadPCHFromAddress: _address.bytes.low++; read_mem(_pc.bytes.high, _address.full); break;
|
||||
|
||||
case CycleReadAndIncrementPC: {
|
||||
uint16_t oldPC = _pc.full;
|
||||
_pc.full++;
|
||||
throwaway_read(oldPC);
|
||||
} break;
|
||||
|
||||
#pragma mark - JAM
|
||||
|
||||
case CycleScheduleJam: {
|
||||
_is_jammed = true;
|
||||
static const MicroOp jam[] = JAM;
|
||||
schedule_program(jam);
|
||||
|
||||
if (_jam_handler) {
|
||||
_jam_handler->processor_did_jam(this, _pc.full - 1);
|
||||
checkSchedule(_is_jammed = false);
|
||||
}
|
||||
} break;
|
||||
|
||||
#pragma mark - Bitwise
|
||||
|
||||
case OperationORA: _a |= _operand; _negativeResult = _zeroResult = _a; break;
|
||||
case OperationAND: _a &= _operand; _negativeResult = _zeroResult = _a; break;
|
||||
case OperationEOR: _a ^= _operand; _negativeResult = _zeroResult = _a; break;
|
||||
|
||||
#pragma mark - Load nad Store
|
||||
|
||||
case OperationLDA: _a = _negativeResult = _zeroResult = _operand; break;
|
||||
case OperationLDX: _x = _negativeResult = _zeroResult = _operand; break;
|
||||
case OperationLDY: _y = _negativeResult = _zeroResult = _operand; break;
|
||||
case OperationLAX: _a = _x = _negativeResult = _zeroResult = _operand; break;
|
||||
|
||||
case OperationSTA: _operand = _a; break;
|
||||
case OperationSTX: _operand = _x; break;
|
||||
case OperationSTY: _operand = _y; break;
|
||||
case OperationSAX: _operand = _a & _x; break;
|
||||
case OperationSHA: _operand = _a & _x & (_address.bytes.high+1); break;
|
||||
case OperationSHX: _operand = _x & (_address.bytes.high+1); break;
|
||||
case OperationSHY: _operand = _y & (_address.bytes.high+1); break;
|
||||
case OperationSHS: _s = _a & _x; _operand = _s & (_address.bytes.high+1); break;
|
||||
|
||||
case OperationLXA:
|
||||
_a = _x = (_a | 0xee) & _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
#pragma mark - Compare
|
||||
|
||||
case OperationCMP: {
|
||||
const uint16_t temp16 = _a - _operand;
|
||||
_negativeResult = _zeroResult = temp16;
|
||||
_carryFlag = ((~temp16) >> 8)&1;
|
||||
} break;
|
||||
case OperationCPX: {
|
||||
const uint16_t temp16 = _x - _operand;
|
||||
_negativeResult = _zeroResult = temp16;
|
||||
_carryFlag = ((~temp16) >> 8)&1;
|
||||
} break;
|
||||
case OperationCPY: {
|
||||
const uint16_t temp16 = _y - _operand;
|
||||
_negativeResult = _zeroResult = temp16;
|
||||
_carryFlag = ((~temp16) >> 8)&1;
|
||||
} break;
|
||||
|
||||
#pragma mark - BIT
|
||||
|
||||
case OperationBIT:
|
||||
_zeroResult = _operand & _a;
|
||||
_negativeResult = _operand;
|
||||
_overflowFlag = _operand&Flag::Overflow;
|
||||
break;
|
||||
|
||||
#pragma mark ADC/SBC (and INS)
|
||||
|
||||
case OperationINS:
|
||||
_operand++; // deliberate fallthrough
|
||||
case OperationSBC:
|
||||
if(_decimalFlag) {
|
||||
const uint16_t notCarry = _carryFlag ^ 0x1;
|
||||
const uint16_t decimalResult = (uint16_t)_a - (uint16_t)_operand - notCarry;
|
||||
uint16_t temp16;
|
||||
|
||||
temp16 = (_a&0xf) - (_operand&0xf) - notCarry;
|
||||
if(temp16 > 0xf) temp16 -= 0x6;
|
||||
temp16 = (temp16&0x0f) | ((temp16 > 0x0f) ? 0xfff0 : 0x00);
|
||||
temp16 += (_a&0xf0) - (_operand&0xf0);
|
||||
|
||||
_overflowFlag = ( ( (decimalResult^_a)&(~decimalResult^_operand) )&0x80) >> 1;
|
||||
_negativeResult = temp16;
|
||||
_zeroResult = decimalResult;
|
||||
|
||||
if(temp16 > 0xff) temp16 -= 0x60;
|
||||
|
||||
_carryFlag = (temp16 > 0xff) ? 0 : Flag::Carry;
|
||||
_a = temp16;
|
||||
break;
|
||||
} else {
|
||||
_operand = ~_operand;
|
||||
}
|
||||
|
||||
// deliberate fallthrough
|
||||
case OperationADC:
|
||||
if(_decimalFlag) {
|
||||
const uint16_t decimalResult = (uint16_t)_a + (uint16_t)_operand + (uint16_t)_carryFlag;
|
||||
uint16_t temp16;
|
||||
|
||||
temp16 = (_a&0xf) + (_operand&0xf) + _carryFlag;
|
||||
if(temp16 > 0x9) temp16 += 0x6;
|
||||
temp16 = (temp16&0x0f) + ((temp16 > 0x0f) ? 0x10 : 0x00) + (_a&0xf0) + (_operand&0xf0);
|
||||
|
||||
_overflowFlag = (( (decimalResult^_a)&(decimalResult^_operand) )&0x80) >> 1;
|
||||
_negativeResult = temp16;
|
||||
_zeroResult = decimalResult;
|
||||
|
||||
if(temp16 > 0x9f) temp16 += 0x60;
|
||||
|
||||
_carryFlag = (temp16 > 0xff) ? Flag::Carry : 0;
|
||||
_a = temp16;
|
||||
} else {
|
||||
const uint16_t decimalResult = (uint16_t)_a + (uint16_t)_operand + (uint16_t)_carryFlag;
|
||||
_overflowFlag = (( (decimalResult^_a)&(decimalResult^_operand) )&0x80) >> 1;
|
||||
_negativeResult = _zeroResult = _a = decimalResult;
|
||||
_carryFlag = (decimalResult >> 8)&1;
|
||||
}
|
||||
|
||||
// fix up in case this was INS
|
||||
if(cycle == OperationINS) _operand = ~_operand;
|
||||
break;
|
||||
|
||||
#pragma mark - Shifts and Rolls
|
||||
|
||||
case OperationASL:
|
||||
_carryFlag = _operand >> 7;
|
||||
_operand <<= 1;
|
||||
_negativeResult = _zeroResult = _operand;
|
||||
break;
|
||||
|
||||
case OperationASO:
|
||||
_carryFlag = _operand >> 7;
|
||||
_operand <<= 1;
|
||||
_a |= _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
case OperationROL: {
|
||||
const uint8_t temp8 = (_operand << 1) | _carryFlag;\
|
||||
_carryFlag = _operand >> 7;\
|
||||
_operand = _negativeResult = _zeroResult = temp8;
|
||||
} break;
|
||||
|
||||
case OperationRLA: {
|
||||
const uint8_t temp8 = (_operand << 1) | _carryFlag;
|
||||
_carryFlag = _operand >> 7;
|
||||
_operand = temp8;
|
||||
_a &= _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
} break;
|
||||
|
||||
case OperationLSR:
|
||||
_carryFlag = _operand & 1;
|
||||
_operand >>= 1;
|
||||
_negativeResult = _zeroResult = _operand;
|
||||
break;
|
||||
|
||||
case OperationLSE:
|
||||
_carryFlag = _operand & 1;
|
||||
_operand >>= 1;
|
||||
_a ^= _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
case OperationASR:
|
||||
_a &= _operand;
|
||||
_carryFlag = _a & 1;
|
||||
_a >>= 1;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
case OperationROR: {
|
||||
const uint8_t temp8 = (_operand >> 1) | (_carryFlag << 7);
|
||||
_carryFlag = _operand & 1;
|
||||
_operand = _negativeResult = _zeroResult = temp8;
|
||||
} break;
|
||||
|
||||
case OperationRRA: {
|
||||
const uint8_t temp8 = (_operand >> 1) | (_carryFlag << 7);
|
||||
_carryFlag = _operand & 1;
|
||||
_operand = temp8;
|
||||
} break;
|
||||
|
||||
case OperationDecrementOperand: _operand--; break;
|
||||
case OperationIncrementOperand: _operand++; break;
|
||||
|
||||
case OperationCLC: _carryFlag = 0; break;
|
||||
case OperationCLI: _interruptFlag = 0; break;
|
||||
case OperationCLV: _overflowFlag = 0; break;
|
||||
case OperationCLD: _decimalFlag = 0; break;
|
||||
|
||||
case OperationSEC: _carryFlag = Flag::Carry; break;
|
||||
case OperationSEI: _interruptFlag = Flag::Interrupt; break;
|
||||
case OperationSED: _decimalFlag = Flag::Decimal; break;
|
||||
|
||||
case OperationINC: _operand++; _negativeResult = _zeroResult = _operand; break;
|
||||
case OperationDEC: _operand--; _negativeResult = _zeroResult = _operand; break;
|
||||
case OperationINX: _x++; _negativeResult = _zeroResult = _x; break;
|
||||
case OperationDEX: _x--; _negativeResult = _zeroResult = _x; break;
|
||||
case OperationINY: _y++; _negativeResult = _zeroResult = _y; break;
|
||||
case OperationDEY: _y--; _negativeResult = _zeroResult = _y; break;
|
||||
|
||||
case OperationANE:
|
||||
_a = (_a | 0xee) & _operand & _x;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
case OperationANC:
|
||||
_a &= _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
_carryFlag = _a >> 7;
|
||||
break;
|
||||
|
||||
case OperationLAS:
|
||||
_a = _x = _s = _s & _operand;
|
||||
_negativeResult = _zeroResult = _a;
|
||||
break;
|
||||
|
||||
#pragma mark - Addressing Mode Work
|
||||
|
||||
case CycleAddXToAddressLow:
|
||||
_nextAddress.full = _address.full + _x;
|
||||
_address.bytes.low = _nextAddress.bytes.low;
|
||||
if (_address.bytes.high != _nextAddress.bytes.high) {
|
||||
throwaway_read(_address.full);
|
||||
}
|
||||
break;
|
||||
case CycleAddYToAddressLow:
|
||||
_nextAddress.full = _address.full + _y;
|
||||
_address.bytes.low = _nextAddress.bytes.low;
|
||||
if (_address.bytes.high != _nextAddress.bytes.high) {
|
||||
throwaway_read(_address.full);
|
||||
}
|
||||
break;
|
||||
case CycleCorrectAddressHigh:
|
||||
_address.full = _nextAddress.full;
|
||||
break;
|
||||
case CycleIncrementPCFetchAddressLowFromOperand:
|
||||
_pc.full++;
|
||||
read_mem(_address.bytes.low, _operand);
|
||||
break;
|
||||
case CycleAddXToOperandFetchAddressLow:
|
||||
_operand += _x;
|
||||
read_mem(_address.bytes.low, _operand);
|
||||
break;
|
||||
case CycleIncrementOperandFetchAddressHigh:
|
||||
_operand++;
|
||||
read_mem(_address.bytes.high, _operand);
|
||||
break;
|
||||
case CycleIncrementPCReadPCHLoadPCL: // deliberate fallthrough
|
||||
_pc.full++;
|
||||
case CycleReadPCHLoadPCL: {
|
||||
uint16_t oldPC = _pc.full;
|
||||
_pc.bytes.low = _operand;
|
||||
read_mem(_pc.bytes.high, oldPC);
|
||||
} break;
|
||||
|
||||
case CycleReadAddressHLoadAddressL:
|
||||
_address.bytes.low = _operand; _pc.full++;
|
||||
read_mem(_address.bytes.high, _pc.full);
|
||||
break;
|
||||
|
||||
case CycleLoadAddressAbsolute: {
|
||||
uint16_t nextPC = _pc.full+1;
|
||||
_pc.full += 2;
|
||||
_address.bytes.low = _operand;
|
||||
read_mem(_address.bytes.high, nextPC);
|
||||
} break;
|
||||
|
||||
case OperationLoadAddressZeroPage:
|
||||
_pc.full++;
|
||||
_address.full = _operand;
|
||||
break;
|
||||
|
||||
case CycleLoadAddessZeroX:
|
||||
_pc.full++;
|
||||
_address.full = (_operand + _x)&0xff;
|
||||
throwaway_read(_operand);
|
||||
break;
|
||||
|
||||
case CycleLoadAddessZeroY:
|
||||
_pc.full++;
|
||||
_address.full = (_operand + _y)&0xff;
|
||||
throwaway_read(_operand);
|
||||
break;
|
||||
|
||||
case OperationIncrementPC: _pc.full++; break;
|
||||
case CycleFetchOperandFromAddress: read_mem(_operand, _address.full); break;
|
||||
case CycleWriteOperandToAddress: write_mem(_operand, _address.full); break;
|
||||
case OperationCopyOperandFromA: _operand = _a; break;
|
||||
case OperationCopyOperandToA: _a = _operand; break;
|
||||
|
||||
#pragma mark - Branching
|
||||
|
||||
#define BRA(condition) _pc.full++; if(condition) schedule_program(doBranch)
|
||||
|
||||
case OperationBPL: BRA(!(_negativeResult&0x80)); break;
|
||||
case OperationBMI: BRA(_negativeResult&0x80); break;
|
||||
case OperationBVC: BRA(!_overflowFlag); break;
|
||||
case OperationBVS: BRA(_overflowFlag); break;
|
||||
case OperationBCC: BRA(!_carryFlag); break;
|
||||
case OperationBCS: BRA(_carryFlag); break;
|
||||
case OperationBNE: BRA(_zeroResult); break;
|
||||
case OperationBEQ: BRA(!_zeroResult); break;
|
||||
|
||||
case CycleAddSignedOperandToPC:
|
||||
_nextAddress.full = _pc.full + (int8_t)_operand;
|
||||
_pc.bytes.low = _nextAddress.bytes.low;
|
||||
if(_nextAddress.bytes.high != _pc.bytes.high) {
|
||||
uint16_t halfUpdatedPc = _pc.full;
|
||||
_pc.full = _nextAddress.full;
|
||||
throwaway_read(halfUpdatedPc);
|
||||
}
|
||||
break;
|
||||
|
||||
#undef BRA
|
||||
|
||||
#pragma mark - Transfers
|
||||
|
||||
case OperationTXA: _zeroResult = _negativeResult = _a = _x; break;
|
||||
case OperationTYA: _zeroResult = _negativeResult = _a = _y; break;
|
||||
case OperationTXS: _s = _x; break;
|
||||
case OperationTAY: _zeroResult = _negativeResult = _y = _a; break;
|
||||
case OperationTAX: _zeroResult = _negativeResult = _x = _a; break;
|
||||
case OperationTSX: _zeroResult = _negativeResult = _x = _s; break;
|
||||
|
||||
case OperationARR:
|
||||
if(_decimalFlag) {
|
||||
_a &= _operand;
|
||||
uint8_t unshiftedA = _a;
|
||||
_a = (_a >> 1) | (_carryFlag << 7);
|
||||
_zeroResult = _negativeResult = _a;
|
||||
_overflowFlag = (_a^(_a << 1))&Flag::Overflow;
|
||||
|
||||
if ((unshiftedA&0xf) + (unshiftedA&0x1) > 5) _a = ((_a + 6)&0xf) | (_a & 0xf0);
|
||||
|
||||
_carryFlag = ((unshiftedA&0xf0) + (unshiftedA&0x10) > 0x50) ? 1 : 0;
|
||||
if (_carryFlag) _a += 0x60;
|
||||
|
||||
} else {
|
||||
_a &= _operand;
|
||||
_a = (_a >> 1) | (_carryFlag << 7);
|
||||
_negativeResult = _zeroResult = _a;
|
||||
_carryFlag = (_a >> 6)&1;
|
||||
_overflowFlag = (_a^(_a << 1))&Flag::Overflow;
|
||||
}
|
||||
break;
|
||||
|
||||
case OperationSBX:
|
||||
_x &= _a;
|
||||
uint16_t difference = _x - _operand;
|
||||
_x = (uint8_t)difference;
|
||||
_negativeResult = _zeroResult = _x;
|
||||
_carryFlag = ((difference >> 8)&1)^1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (_nextBusOperation != BusOperation::None) {
|
||||
static_cast<T *>(this)->perform_bus_operation(_nextBusOperation, _busAddress, _busValue);
|
||||
number_of_cycles--; _nextBusOperation = BusOperation::None;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t get_value_of_register(Register r)
|
||||
{
|
||||
switch (r) {
|
||||
case Register::ProgramCounter: return _pc.full;
|
||||
case Register::LastOperationAddress: return _lastOperationPC.full;
|
||||
case Register::StackPointer: return _s;
|
||||
case Register::Flags: return get_flags();
|
||||
case Register::A: return _a;
|
||||
case Register::S: return _s;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
void set_value_of_register(Register r, uint16_t value)
|
||||
{
|
||||
switch (r) {
|
||||
case Register::ProgramCounter: _pc.full = value; break;
|
||||
case Register::StackPointer: _s = value; break;
|
||||
case Register::Flags: set_flags(value); break;
|
||||
case Register::A: _a = value; break;
|
||||
case Register::S: _s = value; break;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
void reset()
|
||||
{
|
||||
static_cast<T *>(this)->perform_bus_operation(CPU6502::BusOperation::Read, 0xfffc, &_pc.bytes.low);
|
||||
static_cast<T *>(this)->perform_bus_operation(CPU6502::BusOperation::Read, 0xfffd, &_pc.bytes.high);
|
||||
|
||||
// only the interrupt flag is defined upon reset but get_flags isn't going to
|
||||
// mask the other flags so we need to do that, at least
|
||||
_interruptFlag = Flag::Interrupt;
|
||||
_carryFlag &= Flag::Carry;
|
||||
_decimalFlag &= Flag::Decimal;
|
||||
_overflowFlag &= Flag::Overflow;
|
||||
}
|
||||
|
||||
void return_from_subroutine()
|
||||
{
|
||||
_s++;
|
||||
static_cast<T *>(this)->perform_bus_operation(CPU6502::BusOperation::Read, 0x100 | _s, &_pc.bytes.low); _s++;
|
||||
static_cast<T *>(this)->perform_bus_operation(CPU6502::BusOperation::Read, 0x100 | _s, &_pc.bytes.high);
|
||||
_pc.full++;
|
||||
|
||||
if(_is_jammed) {
|
||||
_scheduledPrograms[0] = _scheduledPrograms[1] = _scheduledPrograms[2] = _scheduledPrograms[3] = nullptr;
|
||||
}
|
||||
}
|
||||
|
||||
bool is_jammed()
|
||||
{
|
||||
return _is_jammed;
|
||||
}
|
||||
|
||||
void set_jam_handler(JamHandler *handler)
|
||||
{
|
||||
_jam_handler = handler;
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif /* CPU6502_cpp */
|
||||
33
Processors/6502/CPU6502AllRAM.cpp
Normal file
33
Processors/6502/CPU6502AllRAM.cpp
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
//
|
||||
// CPU6502AllRAM.cpp
|
||||
// ElectrEm
|
||||
//
|
||||
// Created by Thomas Harte on 13/07/2015.
|
||||
// Copyright © 2015 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#include "CPU6502AllRAM.hpp"
|
||||
#include <algorithm>
|
||||
#include <string.h>
|
||||
|
||||
using namespace CPU6502;
|
||||
|
||||
AllRAMProcessor::AllRAMProcessor()
|
||||
{
|
||||
reset();
|
||||
}
|
||||
|
||||
void AllRAMProcessor::perform_bus_operation(CPU6502::BusOperation operation, uint16_t address, uint8_t *value)
|
||||
{
|
||||
if(isReadOperation(operation)) {
|
||||
*value = _memory[address];
|
||||
} else {
|
||||
_memory[address] = *value;
|
||||
}
|
||||
}
|
||||
|
||||
void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data)
|
||||
{
|
||||
size_t endAddress = std::min(startAddress + length, (size_t)65536);
|
||||
memcpy(&_memory[startAddress], data, endAddress - startAddress);
|
||||
}
|
||||
32
Processors/6502/CPU6502AllRAM.hpp
Normal file
32
Processors/6502/CPU6502AllRAM.hpp
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
//
|
||||
// CPU6502AllRAM.hpp
|
||||
// ElectrEm
|
||||
//
|
||||
// Created by Thomas Harte on 13/07/2015.
|
||||
// Copyright © 2015 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef CPU6502AllRAM_cpp
|
||||
#define CPU6502AllRAM_cpp
|
||||
|
||||
#include "CPU6502.hpp"
|
||||
|
||||
namespace CPU6502 {
|
||||
|
||||
class AllRAMProcessor: public Processor<AllRAMProcessor> {
|
||||
|
||||
public:
|
||||
|
||||
AllRAMProcessor();
|
||||
|
||||
void perform_bus_operation(CPU6502::BusOperation operation, uint16_t address, uint8_t *value);
|
||||
|
||||
void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
|
||||
|
||||
private:
|
||||
uint8_t _memory[65536];
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif /* CPU6502AllRAM_cpp */
|
||||
Loading…
Reference in New Issue
Block a user