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Complete instruction set; consolidate mapper.
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Thomas Harte
parent
e986ae2878
commit
6577f68efc
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@ -1,17 +0,0 @@
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//
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// Model.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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namespace InstructionSet::ARM {
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enum class Model {
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ARM2,
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};
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}
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@ -1,68 +0,0 @@
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//
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// Operation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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namespace InstructionSet::ARM {
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enum class Operation {
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/// Rd = Op1 AND Op2.
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AND,
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/// Rd = Op1 EOR Op2.
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EOR,
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/// Rd = Op1 - Op2.
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SUB,
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/// Rd = Op2 - Op1.
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RSB,
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/// Rd = Op1 + Op2.
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ADD,
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/// Rd = Op1 + Ord2 + C.
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ADC,
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/// Rd = Op1 - Op2 + C.
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SBC,
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/// Rd = Op2 - Op1 + C.
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RSC,
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/// Set condition codes on Op1 AND Op2.
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TST,
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/// Set condition codes on Op1 EOR Op2.
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TEQ,
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/// Set condition codes on Op1 - Op2.
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CMP,
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/// Set condition codes on Op1 + Op2.
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CMN,
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/// Rd = Op1 OR Op2.
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ORR,
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/// Rd = Op2
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MOV,
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/// Rd = Op1 AND NOT Op2.
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BIC,
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/// Rd = NOT Op2.
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MVN,
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MUL, MLA,
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B, BL,
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LDR, STR,
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LDM, STM,
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SWI,
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CDP,
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MRC, MCR,
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CoprocessorDataTransfer,
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Undefined,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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}
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@ -1,5 +1,5 @@
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//
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// Decoder.hpp
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// OperationMapper.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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@ -8,15 +8,69 @@
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#pragma once
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#include "Model.hpp"
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#include "Operation.hpp"
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#include "../../Reflection/Dispatcher.hpp"
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#include <array>
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namespace InstructionSet::ARM {
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enum class Model {
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ARM2,
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};
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enum class Operation {
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/// Rd = Op1 AND Op2.
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AND,
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/// Rd = Op1 EOR Op2.
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EOR,
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/// Rd = Op1 - Op2.
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SUB,
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/// Rd = Op2 - Op1.
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RSB,
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/// Rd = Op1 + Op2.
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ADD,
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/// Rd = Op1 + Ord2 + C.
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ADC,
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/// Rd = Op1 - Op2 + C.
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SBC,
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/// Rd = Op2 - Op1 + C.
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RSC,
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/// Set condition codes on Op1 AND Op2.
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TST,
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/// Set condition codes on Op1 EOR Op2.
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TEQ,
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/// Set condition codes on Op1 - Op2.
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CMP,
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/// Set condition codes on Op1 + Op2.
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CMN,
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/// Rd = Op1 OR Op2.
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ORR,
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/// Rd = Op2
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MOV,
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/// Rd = Op1 AND NOT Op2.
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BIC,
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/// Rd = NOT Op2.
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MVN,
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MUL, MLA,
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B, BL,
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LDR, STR,
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LDM, STM,
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SWI,
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CDP,
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MRC, MCR,
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LDC, STC,
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Undefined,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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enum class ShiftType {
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LogicalLeft = 0b00,
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LogicalRight = 0b01,
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@ -204,10 +258,41 @@ struct CoprocessorOperationOrRegisterTransfer {
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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protected:
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor data transfer.
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//
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struct CoprocessorDataTransferFlags {
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constexpr CoprocessorDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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constexpr bool pre_index() { return flag_bit<24>(flags_); }
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constexpr bool add_offset() { return flag_bit<23>(flags_); }
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constexpr bool transfer_length() { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataTransfer {
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constexpr CoprocessorDataTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int base() { return (opcode_ >> 16) & 0xf; }
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int source() { return (opcode_ >> 12) & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int offset() { return opcode_ & 0xff; }
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private:
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uint32_t opcode_;
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};
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/// Operation mapper; use the free function @c dispatch as defined below.
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struct OperationMapper {
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template <int i, typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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constexpr auto partial = uint32_t(i << 20);
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@ -304,6 +389,16 @@ struct OperationMapper {
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);
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}
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}
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// Coprocessor data transfers; cf. p.39.
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if constexpr (((partial >> 25) & 0b111) == 0b110) {
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constexpr bool is_ldc = partial & (1 << 20);
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constexpr auto flags = CoprocessorDataTransferFlags(i);
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scheduler.template coprocessor_data_transfer<is_ldc ? Operation::LDC : Operation::STC, flags>(
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condition,
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CoprocessorDataTransfer(instruction)
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);
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}
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}
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};
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@ -313,12 +408,4 @@ template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &s
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Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
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}
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/*
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if(((opcode >> 25) & 0b111) == 0b110) {
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result[c] = Operation::CoprocessorDataTransfer;
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continue;
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}
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*/
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}
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@ -1333,10 +1333,8 @@
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4B1EC714255398B000A1F44B /* Sound.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Sound.cpp; sourceTree = "<group>"; };
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4B1EC715255398B000A1F44B /* Sound.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Sound.hpp; sourceTree = "<group>"; };
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4B1EDB431E39A0AC009D6819 /* chip.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = chip.png; sourceTree = "<group>"; };
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4B2005402B804AA300420C5C /* Decoder.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Decoder.hpp; sourceTree = "<group>"; };
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4B2005402B804AA300420C5C /* OperationMapper.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = OperationMapper.hpp; sourceTree = "<group>"; };
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4B2005422B804D6400420C5C /* ARMDecoderTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = ARMDecoderTests.mm; sourceTree = "<group>"; };
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4B2005442B804DC900420C5C /* Model.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Model.hpp; sourceTree = "<group>"; };
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4B2005452B804DF600420C5C /* Operation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Operation.hpp; sourceTree = "<group>"; };
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4B2130E0273A7A0A008A77B4 /* Audio.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Audio.cpp; sourceTree = "<group>"; };
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4B2130E1273A7A0A008A77B4 /* Audio.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Audio.hpp; sourceTree = "<group>"; };
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4B228CD424D773B30077EF25 /* CSScanTarget.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = CSScanTarget.mm; sourceTree = "<group>"; };
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@ -2760,9 +2758,7 @@
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4B20053D2B804A4F00420C5C /* ARM */ = {
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isa = PBXGroup;
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children = (
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4B2005402B804AA300420C5C /* Decoder.hpp */,
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4B2005442B804DC900420C5C /* Model.hpp */,
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4B2005452B804DF600420C5C /* Operation.hpp */,
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4B2005402B804AA300420C5C /* OperationMapper.hpp */,
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);
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path = ARM;
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sourceTree = "<group>";
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