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https://github.com/TomHarte/CLK.git
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Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
This commit is contained in:
Thomas Harte
parent
627b96f73c
commit
67fd6787a6
@ -917,6 +917,7 @@
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@ -3964,6 +3966,7 @@
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4B2AF8681E513FC20027EE29 /* TIATests.mm */,
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4B1D08051E0F7A1100763741 /* TimeTests.mm */,
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4BEE4BD325A26E2B00011BD2 /* x86DecoderTests.mm */,
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4BDA8234261E8E000021AA19 /* Z80ContentionTests.mm */,
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4BB73EB81B587A5100552FC2 /* Info.plist */,
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4BC9E1ED1D23449A003FCEE4 /* 6502InterruptTests.swift */,
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4B92EAC91B7C112B00246143 /* 6502TimingTests.swift */,
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@ -5649,6 +5652,7 @@
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4B9D0C4B22C7D70A00DE1AD3 /* 68000BCDTests.mm in Sources */,
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4B778F5E23A5F3230000D260 /* Oric.cpp in Sources */,
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4B3BA0C31D318AEC005DD7A7 /* C1540Tests.swift in Sources */,
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4BDA8235261E8E000021AA19 /* Z80ContentionTests.mm in Sources */,
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4B778F1A23A5ED320000D260 /* Video.cpp in Sources */,
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4B778F3B23A5F1650000D260 /* KeyboardMachine.cpp in Sources */,
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4B778F2E23A5F09E0000D260 /* IRQDelegatePortHandler.cpp in Sources */,
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194
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
Normal file
194
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
Normal file
@ -0,0 +1,194 @@
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//
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// Z80ContentionTests.cpp
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// Clock SignalTests
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//
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// Created by Thomas Harte on 7/4/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../Processors/Z80/Z80.hpp"
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namespace {
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static constexpr uint16_t initial_pc = 0;
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struct CapturingZ80: public CPU::Z80::BusHandler {
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CapturingZ80(const std::initializer_list<uint8_t> &code) : z80_(*this) {
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// Take a copy of the code.
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std::copy(code.begin(), code.end(), ram_);
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// Skip the three cycles the Z80 spends on a reset, and
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// purge them from the record.
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run_for(3);
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bus_records_.clear();
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// Set the refresh address to the EE page.
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z80_.set_value_of_register(CPU::Z80::Register::I, 0xe0);
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}
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void run_for(int cycles) {
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z80_.run_for(HalfCycles(Cycles(cycles)));
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}
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/// A record of the state of the address bus, MREQ, IOREQ and RFSH lines,
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/// upon every clock transition.
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struct BusRecord {
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uint16_t address = 0xffff;
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bool mreq = false, ioreq = false, refresh = false;
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};
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HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Log the activity.
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const uint8_t* const bus_state = cycle.bus_state();
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for(int c = 0; c < cycle.length.as<int>(); c++) {
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bus_records_.emplace_back();
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// TODO: I think everything tested here should have an address,
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// but am currently unsure whether the reset program puts the
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// address bus in high impedance, as bus req/ack does.
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if(cycle.address) {
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bus_records_.back().address = *cycle.address;
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}
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bus_records_.back().mreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::MREQ;
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bus_records_.back().ioreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::IOREQ;
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bus_records_.back().refresh = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::RFSH;
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}
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// Provide only reads.
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if(
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cycle.operation == CPU::Z80::PartialMachineCycle::Read ||
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cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode
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) {
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*cycle.value = ram_[*cycle.address];
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}
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return HalfCycles(0);
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}
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const std::vector<BusRecord> &bus_records() const {
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return bus_records_;
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}
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std::vector<BusRecord> cycle_records() const {
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std::vector<BusRecord> cycle_records;
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for(size_t c = 0; c < bus_records_.size(); c += 2) {
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cycle_records.push_back(bus_records_[c]);
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}
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return cycle_records;
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}
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private:
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CPU::Z80::Processor<CapturingZ80, false, false> z80_;
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uint8_t ram_[65536];
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std::vector<BusRecord> bus_records_;
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};
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}
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@interface Z80ContentionTests : XCTestCase
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@end
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/*!
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Tests the Z80's MREQ, IOREQ and address outputs for correlation to those
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observed by ZX Spectrum users in the software-side documentation of
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contended memory timings.
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*/
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@implementation Z80ContentionTests {
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}
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struct ContentionCheck {
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uint16_t address;
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int length;
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};
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/*!
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Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
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processed by a Sinclair 48k or 128k ULA.
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*/
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- (void)validate48Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
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// 48[/128]k contention logic: triggered on address alone, _unless_
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// MREQ is also active.
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//
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// I think the source I'm using also implicitly assumes that refresh
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// addresses are outside of the contended area, and doesn't check them.
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// So unlike the actual ULA I'm also ignoring any address while refresh
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// is asserted.
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int count = -1;
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uint16_t address = 0;
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auto contention = contentions.begin();
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const auto bus_records = z80.cycle_records();
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for(const auto &record: bus_records) {
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++count;
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if(
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!count || // i.e. is at start.
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(&record == &bus_records.back()) || // i.e. is at end.
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!(record.mreq || record.refresh) // i.e. beginning of a new contention.
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) {
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if(count) {
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XCTAssertNotEqual(contention, contentions.end());
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XCTAssertEqual(contention->address, address);
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XCTAssertEqual(contention->length, count);
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++contention;
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}
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count = 1;
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address = record.address;
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}
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}
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XCTAssertEqual(contention, contentions.end());
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}
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/*!
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Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
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processed by an Amstrad gate array.
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*/
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- (void)validatePlus3Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
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// +3 contention logic: triggered by the leading edge of MREQ, sans refresh.
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int count = -1;
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uint16_t address = 0;
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auto contention = contentions.begin();
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const auto bus_records = z80.bus_records();
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for(size_t c = 0; c < bus_records.size(); c += 2) {
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const bool is_leading_edge = !bus_records[c].mreq && bus_records[c+1].mreq && !bus_records[c].refresh;
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++count;
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if(
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!count || // i.e. is at start.
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(c == bus_records.size() - 2) || // i.e. is at end.
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is_leading_edge // i.e. beginning of a new contention.
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) {
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if(count) {
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XCTAssertNotEqual(contention, contentions.end());
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XCTAssertEqual(contention->address, address);
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XCTAssertEqual(contention->length, count);
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++contention;
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}
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count = 1;
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address = bus_records[c].address;
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}
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}
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XCTAssertEqual(contention, contentions.end());
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}
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// MARK: - Opcode tests.
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- (void)testNOP {
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CapturingZ80 z80({0x00});
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z80.run_for(4);
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[self validate48Contention:{{initial_pc, 4}} z80:z80];
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[self validatePlus3Contention:{{initial_pc, 4}} z80:z80];
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}
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@end
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