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Flushes before set_last_contended_area_access.

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This commit is contained in:
Thomas Harte 2021-03-31 22:52:41 -04:00
parent 4f80523828
commit 687c05365e
1 changed files with 25 additions and 19 deletions
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34
Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp
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@ -185,24 +185,31 @@ template<Model model> class ConcreteMachine:
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) { forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
using PartialMachineCycle = CPU::Z80::PartialMachineCycle; using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
HalfCycles delay(0);
const uint16_t address = cycle.address ? *cycle.address : 0x0000; const uint16_t address = cycle.address ? *cycle.address : 0x0000;
switch(cycle.operation) { if(
default: break; is_contended_[address >> 14] &&
cycle.operation >= PartialMachineCycle::ReadOpcodeStart &&
case PartialMachineCycle::ReadOpcodeStart: cycle.operation <= PartialMachineCycle::WriteStart) {
case PartialMachineCycle::ReadStart:
case PartialMachineCycle::WriteStart:
// Apply contention if necessary. // Apply contention if necessary.
// //
// Assumption here: the trigger for the ULA inserting a delay is the falling edge // Assumption here: the trigger for the ULA inserting a delay is the falling edge
// of MREQ, which is always half a cycle into a read or write. // of MREQ, which is always half a cycle into a read or write.
// //
// TODO: somehow provide that information in the PartialMachineCycle? // TODO: somehow provide that information in the PartialMachineCycle?
if(is_contended_[address >> 14]) {
delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1)); const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1));
advance(cycle.length + delay);
return delay;
} }
break;
// TODO: for read/write this should advance only until the rising edge of MREQ, then do
// the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended
// timings am I now learning what happens with MREQ during extended read/write bus cycles
// (i.e. those longer than 3 cycles)
advance(cycle.length);
switch(cycle.operation) {
default: break;
case PartialMachineCycle::ReadOpcode: case PartialMachineCycle::ReadOpcode:
// Fast loading: ROM version. // Fast loading: ROM version.
@ -225,7 +232,7 @@ template<Model model> class ConcreteMachine:
*cycle.value = read_pointers_[address >> 14][address]; *cycle.value = read_pointers_[address >> 14][address];
if(is_contended_[address >> 14]) { if(is_contended_[address >> 14]) {
video_.last_valid()->set_last_contended_area_access(*cycle.value); video_->set_last_contended_area_access(*cycle.value);
} }
break; break;
@ -239,7 +246,7 @@ template<Model model> class ConcreteMachine:
// Fill the floating bus buffer if this write is within the contended area. // Fill the floating bus buffer if this write is within the contended area.
if(is_contended_[address >> 14]) { if(is_contended_[address >> 14]) {
video_.last_valid()->set_last_contended_area_access(*cycle.value); video_->set_last_contended_area_access(*cycle.value);
} }
break; break;
@ -357,8 +364,7 @@ template<Model model> class ConcreteMachine:
break; break;
} }
advance(cycle.length + delay); return HalfCycles(0);
return delay;
} }
private: private: