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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 08:31:11 +00:00

After all that, it seems likely that inputs just aren't inverted for the Vic.

This commit is contained in:
Thomas Harte 2016-07-09 20:03:38 -04:00
parent 656cd211d7
commit 693c8b2438
3 changed files with 11 additions and 4 deletions

View File

@ -78,8 +78,8 @@ class SerialPortVIA: public MOS::MOS6522<SerialPortVIA>, public MOS::MOS6522IRQD
std::shared_ptr<::Commodore::Serial::Port> serialPort = _serialPort.lock();
if(serialPort) {
serialPort->set_output(::Commodore::Serial::Line::Data,
(::Commodore::Serial::LineLevel)!(_data_level_output
|| (_attention_level_input == _attention_acknowledge_level)));
(::Commodore::Serial::LineLevel)(!_data_level_output
&& (_attention_level_input != _attention_acknowledge_level)));
}
}
};

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@ -78,6 +78,13 @@ Machine::~Machine()
unsigned int Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t address, uint8_t *value)
{
static int logCount = 0;
if(operation == CPU6502::BusOperation::ReadOpcode && address == 0xee17) logCount = 500;
if(operation == CPU6502::BusOperation::ReadOpcode && logCount) {
logCount--;
printf("%04x\n", address);
}
// run the phase-1 part of this cycle, in which the VIC accesses memory
uint16_t video_address = _mos6560->get_address();
uint8_t video_value = _videoMemoryMap[video_address >> 10] ? _videoMemoryMap[video_address >> 10][video_address & 0x3ff] : 0xff; // TODO

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@ -79,8 +79,8 @@ class UserPortVIA: public MOS::MOS6522<UserPortVIA>, public MOS::MOS6522IRQDeleg
// printf("VIC Serial port line %d: %s\n", line, value ? "on" : "off");
switch(line) {
default: break;
case ::Commodore::Serial::Line::Data: _portA = (_portA & ~0x02) | (value ? 0 : 0x02); break;
case ::Commodore::Serial::Line::Clock: _portA = (_portA & ~0x01) | (value ? 0 : 0x01); break;
case ::Commodore::Serial::Line::Data: _portA = (_portA & ~0x02) | (value ? 0x02 : 0x00); break;
case ::Commodore::Serial::Line::Clock: _portA = (_portA & ~0x01) | (value ? 0x01 : 0x00); break;
}
}