diff --git a/OSBindings/Mac/Clock SignalTests/QLTests.mm b/OSBindings/Mac/Clock SignalTests/QLTests.mm
index 3f278b645..779677325 100644
--- a/OSBindings/Mac/Clock SignalTests/QLTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/QLTests.mm	
@@ -11,6 +11,9 @@
 #include <array>
 #include <cassert>
 
+#include <iostream>
+#include <fstream>
+
 #include "68000.hpp"
 #include "CSROMFetcher.hpp"
 
@@ -107,6 +110,8 @@ class QL: public CPU::MC68000::BusHandler {
 	std::unique_ptr<QL> _machine;
 }
 
+std::streambuf *coutbuf;
+
 - (void)setUp {
     const auto roms = CSROMFetcher()("SinclairQL", {"js.rom"});
     _machine.reset(new QL(*roms[0]));
diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index 8455b7999..6cfa2b656 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -52,7 +52,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 						// no instruction was ongoing. Either way, do a standard instruction operation.
 
 						// TODO: unless an interrupt is pending, or the trap flag is set.
-						static bool should_log = false;
+//						static bool should_log = false;
 
 //						should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
 //						if(should_log) {
@@ -654,7 +654,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 										offset = 15;
 										start_address -= 2;
 										write_address_sequence_long(dec_action, 2);
-										movem_final_address_ = start_address;
+										movem_final_address_ = start_address + 2;
 									} else {
 										write_address_sequence_long(inc_action, 0);
 									}