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Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.

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This commit is contained in:
Thomas Harte 2017-08-26 12:59:59 -04:00
parent 1017bb9f6b
commit 6e99169348
2 changed files with 12 additions and 16 deletions
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13
Components/6845/CRTC6845.hpp
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@ -41,18 +41,18 @@ enum Personality {
template <class T> class CRTC6845 {
public:
CRTC6845(Personality p, T &bus_handler) :
CRTC6845(Personality p, T &bus_handler) noexcept :
personality_(p), bus_handler_(bus_handler) {}
void select_register(uint8_t r) {
selected_register_ = r;
}
uint8_t get_status() {
uint8_t get_status() const {
return 0xff;
}
uint8_t get_register() {
uint8_t get_register() const {
if(selected_register_ < 12 || selected_register_ > 17) return 0xff;
return registers_[selected_register_];
}
@ -73,9 +73,6 @@ template <class T> class CRTC6845 {
}
void run_for(Cycles cycles) {
static int c = 0;
c++;
int cyles_remaining = cycles.as_int();
while(cyles_remaining--) {
// check for end of horizontal sync
@ -112,6 +109,10 @@ template <class T> class CRTC6845 {
}
}
const BusState &get_bus_state() const {
return bus_state_;
}
private:
inline void perform_bus_cycle() {
bus_state_.display_enable = character_is_visible_ && line_is_visible_;

15
Machines/AmstradCPC/AmstradCPC.cpp
View File

@ -327,11 +327,6 @@ class CRTCBusHandler {
next_mode_ = mode;
}
/// @returns the current value of the CRTC's vertical sync output.
bool get_vsync() const {
return was_vsync_;
}
/// Palette management: selects a pen to modify.
void select_pen(int pen) {
pen_ = pen;
@ -597,11 +592,11 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
public:
i8255PortHandler(
KeyboardState &key_state,
const CRTCBusHandler &crtc_bus_handler,
const Motorola::CRTC::CRTC6845<CRTCBusHandler> &crtc,
AYDeferrer &ay,
Storage::Tape::BinaryTapePlayer &tape_player) :
key_state_(key_state),
crtc_bus_handler_(crtc_bus_handler),
crtc_(crtc),
ay_(ay),
tape_player_(tape_player) {}
@ -642,7 +637,7 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
switch(port) {
case 0: return ay_.ay()->get_data_output(); // Port A is wired to the AY
case 1: return
(crtc_bus_handler_.get_vsync() ? 0x01 : 0x00) | // Bit 0 returns CRTC vsync.
(crtc_.get_bus_state().vsync ? 0x01 : 0x00) | // Bit 0 returns CRTC vsync.
(tape_player_.get_input() ? 0x80 : 0x00) | // Bit 7 returns cassette input.
0x7e; // Bits unimplemented:
//
@ -657,7 +652,7 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
private:
AYDeferrer &ay_;
KeyboardState &key_state_;
const CRTCBusHandler &crtc_bus_handler_;
const Motorola::CRTC::CRTC6845<CRTCBusHandler> &crtc_;
Storage::Tape::BinaryTapePlayer &tape_player_;
};
@ -676,7 +671,7 @@ class ConcreteMachine:
crtc_(Motorola::CRTC::HD6845S, crtc_bus_handler_),
crtc_bus_handler_(ram_, interrupt_timer_),
i8255_(i8255_port_handler_),
i8255_port_handler_(key_state_, crtc_bus_handler_, ay_, tape_player_),
i8255_port_handler_(key_state_, crtc_, ay_, tape_player_),
tape_player_(8000000) {
// primary clock is 4Mhz
set_clock_rate(4000000);