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Pull unrecognised instruction handling into the usual switch table.

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This commit is contained in:
Thomas Harte 2022-05-24 12:42:34 -04:00
parent 0dfaa7d9cf
commit 6f048de973
1 changed files with 16 additions and 16 deletions
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32
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -503,22 +503,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToStateSpecific(StandardException); MoveToStateSpecific(StandardException);
} }
// Check for an unrecognised opcode.
if(instruction_.operation == InstructionSet::M68k::Operation::Undefined) {
switch(opcode_ & 0xf000) {
default:
exception_vector_ = InstructionSet::M68k::Exception::IllegalInstruction;
break;
case 0xa000:
exception_vector_ = InstructionSet::M68k::Exception::Line1010;
break;
case 0xf000:
exception_vector_ = InstructionSet::M68k::Exception::Line1111;
break;
}
MoveToStateSpecific(StandardException);
}
// Ensure the first parameter is next fetched. // Ensure the first parameter is next fetched.
next_operand_ = 0; next_operand_ = 0;
@ -556,6 +540,22 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
#define SpecialCASE(x) case InstructionSet::M68k::Operation::x: MoveToStateSpecific(x) #define SpecialCASE(x) case InstructionSet::M68k::Operation::x: MoveToStateSpecific(x)
switch(instruction_.operation) { switch(instruction_.operation) {
CASE(Undefined)
if(instruction_.operation == InstructionSet::M68k::Operation::Undefined) {
switch(opcode_ & 0xf000) {
default:
exception_vector_ = InstructionSet::M68k::Exception::IllegalInstruction;
break;
case 0xa000:
exception_vector_ = InstructionSet::M68k::Exception::Line1010;
break;
case 0xf000:
exception_vector_ = InstructionSet::M68k::Exception::Line1111;
break;
}
MoveToStateSpecific(StandardException);
}
StdCASE(NBCD, { StdCASE(NBCD, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) { if(instruction_.mode(0) == Mode::DataRegisterDirect) {
perform_state_ = Perform_np_n; perform_state_ = Perform_np_n;