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https://github.com/TomHarte/CLK.git
synced 2024-10-18 08:24:17 +00:00
Made an initial stab at outputting half the correct pixels.
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@ -23,9 +23,9 @@ Machine::Machine() :
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}
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}
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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cycles_since_display_update_ += cycle.length;
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cycles_since_display_update_ += (unsigned int)cycle.length;
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uint8_t r;
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uint16_t r = 0;
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uint16_t address = cycle.address ? *cycle.address : 0;
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uint16_t address = cycle.address ? *cycle.address : 0;
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switch(cycle.operation) {
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switch(cycle.operation) {
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case CPU::Z80::BusOperation::Output:
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case CPU::Z80::BusOperation::Output:
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@ -37,24 +37,32 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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case CPU::Z80::BusOperation::Input:
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case CPU::Z80::BusOperation::Input:
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if((address&7) == 6) {
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if((address&7) == 6) {
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set_vsync(true);
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set_vsync(true);
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line_counter_ = 0;
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}
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}
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*cycle.value = 0xff;
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*cycle.value = 0xff;
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break;
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break;
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case CPU::Z80::BusOperation::Interrupt:
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case CPU::Z80::BusOperation::Interrupt:
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set_hsync(true);
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set_hsync(true);
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line_counter_ = (line_counter_ + 1) & 7;
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*cycle.value = 0xff;
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*cycle.value = 0xff;
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break;
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break;
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case CPU::Z80::BusOperation::ReadOpcode:
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case CPU::Z80::BusOperation::ReadOpcode:
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set_hsync(false);
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set_hsync(false);
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r = (uint8_t)get_value_of_register(CPU::Z80::Register::R);
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r = (uint8_t)get_value_of_register(CPU::Z80::Register::Refresh);
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set_interrupt_line(!(r & 0x40));
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set_interrupt_line(!(r & 0x40));
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case CPU::Z80::BusOperation::Read:
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case CPU::Z80::BusOperation::Read:
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if((address & 0xc000) == 0x0000) *cycle.value = rom_[address & (rom_.size() - 1)];
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if((address & 0xc000) == 0x0000) *cycle.value = rom_[address & (rom_.size() - 1)];
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else if((address & 0x4000) == 0x4000) {
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else if((address & 0x4000) == 0x4000) {
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uint8_t value = ram_[address & 1023];
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uint8_t value = ram_[address & 1023];
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if(address&0x8000 && !(value & 0x40) && cycle.operation == CPU::Z80::BusOperation::ReadOpcode && !get_halt_line()) {
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if(address&0x8000 && !(value & 0x40) && cycle.operation == CPU::Z80::BusOperation::ReadOpcode && !get_halt_line()) {
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size_t char_address = (size_t)((r & 0xff00) | ((value & 0x3f) << 3) | line_counter_);
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if((char_address & 0xc000) == 0x0000) {
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uint8_t mask = (value & 0x80) ? 0xff : 0x00;
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value = rom_[char_address & (rom_.size() - 1)] ^ mask;
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}
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// TODO: character lookup.
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// TODO: character lookup.
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output_byte(value);
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output_byte(value);
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*cycle.value = 0;
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*cycle.value = 0;
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@ -154,8 +162,8 @@ void Machine::output_level(unsigned int number_of_cycles) {
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}
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}
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void Machine::output_data() {
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void Machine::output_data() {
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unsigned int data_length = (unsigned int)(line_data_pointer_ - line_data_);
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unsigned int data_length = ((unsigned int)(line_data_pointer_ - line_data_)) ;
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crt_->output_data(data_length, 1);
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crt_->output_data(data_length * 1, 1);
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line_data_pointer_ = line_data_ = nullptr;
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line_data_pointer_ = line_data_ = nullptr;
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cycles_since_display_update_ -= data_length;
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cycles_since_display_update_ -= data_length;
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}
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}
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@ -175,10 +183,11 @@ void Machine::output_byte(uint8_t byte) {
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}
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}
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if(line_data_) {
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if(line_data_) {
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line_data_pointer_[0] = byte;
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uint8_t mask = 0x80;
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line_data_pointer_[1] = byte;
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for(int c = 0; c < 4; c++) {
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line_data_pointer_[2] = byte;
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line_data_pointer_[c] = (byte & mask) ? 0xff : 0x00;
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line_data_pointer_[3] = byte;
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mask >>= 1;
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}
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line_data_pointer_ += 4;
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line_data_pointer_ += 4;
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}
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}
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}
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}
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@ -53,6 +53,7 @@ class Machine:
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bool vsync_, hsync_;
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bool vsync_, hsync_;
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bool is_sync_;
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bool is_sync_;
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uint8_t *line_data_, *line_data_pointer_;
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uint8_t *line_data_, *line_data_pointer_;
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int line_counter_;
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unsigned int cycles_since_display_update_;
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unsigned int cycles_since_display_update_;
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void update_display();
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void update_display();
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