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https://github.com/TomHarte/CLK.git
synced 2025-04-14 18:37:11 +00:00
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
This commit is contained in:
parent
d559d8b901
commit
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@ -412,6 +412,7 @@
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4BF829631D8F536B001BAE39 /* SSD.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829611D8F536B001BAE39 /* SSD.cpp */; };
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4BF829661D8F732B001BAE39 /* Disk.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829641D8F732B001BAE39 /* Disk.cpp */; };
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4BFCA1201ECBDC1500AC40C1 /* Z80AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */; };
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4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */; };
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/* End PBXBuildFile section */
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/* Begin PBXContainerItemProxy section */
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@ -975,6 +976,8 @@
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4BF829681D8F7361001BAE39 /* File.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = File.hpp; path = ../../StaticAnalyser/Acorn/File.hpp; sourceTree = "<group>"; };
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4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Z80AllRAM.cpp; path = Z80/Z80AllRAM.cpp; sourceTree = "<group>"; };
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4BFCA11E1ECBD9BD00AC40C1 /* Z80AllRAM.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Z80AllRAM.hpp; path = Z80/Z80AllRAM.hpp; sourceTree = "<group>"; };
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4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = AllRAMProcessor.cpp; sourceTree = "<group>"; };
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4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = AllRAMProcessor.hpp; sourceTree = "<group>"; };
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/* End PBXFileReference section */
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/* Begin PBXFrameworksBuildPhase section */
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@ -1813,6 +1816,8 @@
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4B77069E1EC9045B0053B588 /* Z80 */,
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4B7706A01EC9398D0053B588 /* MicroOpScheduler.hpp */,
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4B2C455C1EC9442600FC74DD /* RegisterSizes.hpp */,
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4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */,
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4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */,
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);
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name = Processors;
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path = ../../Processors;
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@ -2551,6 +2556,7 @@
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4BC9E1EE1D23449A003FCEE4 /* 6502InterruptTests.swift in Sources */,
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4BEF6AAA1D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm in Sources */,
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4B924E991E74D22700B76AF1 /* AtariStaticAnalyserTests.mm in Sources */,
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4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */,
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4B50730A1DDFCFDF00C48FBD /* ArrayBuilderTests.mm in Sources */,
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4B2AF8691E513FC20027EE29 /* TIATests.mm in Sources */,
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4B3BA0CE1D318B44005DD7A7 /* C1540Bridge.mm in Sources */,
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@ -12,9 +12,7 @@
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using namespace CPU::MOS6502;
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AllRAMProcessor::AllRAMProcessor() : _timestamp(0) {
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set_power_on(false);
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}
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AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
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int AllRAMProcessor::perform_bus_operation(MOS6502::BusOperation operation, uint16_t address, uint8_t *value) {
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timestamp_++;
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@ -27,12 +25,3 @@ int AllRAMProcessor::perform_bus_operation(MOS6502::BusOperation operation, uint
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return 1;
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}
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void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
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size_t endAddress = std::min(startAddress + length, (size_t)65536);
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memcpy(&memory_[startAddress], data, endAddress - startAddress);
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}
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uint32_t AllRAMProcessor::get_timestamp() {
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return timestamp_;
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}
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@ -10,22 +10,19 @@
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#define MOS6502AllRAM_cpp
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#include "6502.hpp"
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#include "../AllRAMProcessor.hpp"
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namespace CPU {
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namespace MOS6502 {
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class AllRAMProcessor: public Processor<AllRAMProcessor> {
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class AllRAMProcessor:
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public ::CPU::AllRAMProcessor,
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public Processor<AllRAMProcessor> {
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public:
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AllRAMProcessor();
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int perform_bus_operation(MOS6502::BusOperation operation, uint16_t address, uint8_t *value);
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void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
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uint32_t get_timestamp();
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private:
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uint8_t memory_[65536];
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uint32_t timestamp_;
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};
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}
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24
Processors/AllRAMProcessor.cpp
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24
Processors/AllRAMProcessor.cpp
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@ -0,0 +1,24 @@
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//
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// AllRAMProcessor.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "AllRAMProcessor.hpp"
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using namespace CPU;
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AllRAMProcessor::AllRAMProcessor(size_t memory_size) :
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memory_(memory_size),
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timestamp_(0) {}
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void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
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size_t endAddress = std::min(startAddress + length, (size_t)65536);
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memcpy(&memory_[startAddress], data, endAddress - startAddress);
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}
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uint32_t AllRAMProcessor::get_timestamp() {
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return timestamp_;
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}
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30
Processors/AllRAMProcessor.hpp
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30
Processors/AllRAMProcessor.hpp
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@ -0,0 +1,30 @@
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//
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// AllRAMProcessor.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#ifndef AllRAMProcessor_hpp
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#define AllRAMProcessor_hpp
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#include <cstdint>
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#include <vector>
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namespace CPU {
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class AllRAMProcessor {
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public:
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AllRAMProcessor(size_t memory_size);
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uint32_t get_timestamp();
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void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
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protected:
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std::vector<uint8_t> memory_;
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uint32_t timestamp_;
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};
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}
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#endif /* AllRAMProcessor_hpp */
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@ -11,17 +11,8 @@
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using namespace CPU::Z80;
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AllRAMProcessor::AllRAMProcessor() {}
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AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
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int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
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return 0;
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}
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void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
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size_t endAddress = std::min(startAddress + length, (size_t)65536);
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memcpy(&memory_[startAddress], data, endAddress - startAddress);
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}
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uint32_t AllRAMProcessor::get_timestamp() {
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return timestamp_;
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}
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@ -10,22 +10,19 @@
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#define Z80AllRAM_hpp
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#include "Z80.hpp"
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#include "../AllRAMProcessor.hpp"
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namespace CPU {
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namespace Z80 {
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class AllRAMProcessor: public Processor<AllRAMProcessor> {
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class AllRAMProcessor:
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public ::CPU::AllRAMProcessor,
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public Processor<AllRAMProcessor> {
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public:
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AllRAMProcessor();
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int perform_machine_cycle(const MachineCycle *cycle);
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void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
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uint32_t get_timestamp();
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private:
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uint8_t memory_[65536];
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uint32_t timestamp_;
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};
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}
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