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https://github.com/TomHarte/CLK.git
synced 2025-09-25 08:25:09 +00:00
Add a ticking-but-diconnected CRTC.
This commit is contained in:
Thomas Harte
@@ -11,12 +11,14 @@
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#include "Machines/MachineTypes.hpp"
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#include "Components/6522/6522.hpp"
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#include "Components/6845/CRTC6845.hpp"
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#include "Components/SN76489/SN76489.hpp"
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#include "Processors/6502/6502.hpp"
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#include "Analyser/Static/Acorn/Target.hpp"
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#include "Outputs/Log.hpp"
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#include "Outputs/CRT/CRT.hpp"
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#include "Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "Concurrency/AsyncTaskQueue.hpp"
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@@ -30,6 +32,9 @@ namespace BBCMicro {
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namespace {
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using Logger = Log::Logger<Log::Source::BBCMicro>;
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/*!
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Combines an SN76489 with an appropriate asynchronous queue and filtering speaker.
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*/
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struct Audio {
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Audio() :
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sn76489_(TI::SN76489::Personality::SN76489, audio_queue_),
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@@ -68,9 +73,15 @@ private:
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HalfCycles time_since_update_;
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};
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/*!
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Models the user-port VIA.
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*/
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struct UserVIAPortHandler: public MOS::MOS6522::IRQDelegatePortHandler {
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};
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/*!
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Models the system VIA, which connects to the SN76489 and the keyboard.
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*/
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struct SystemVIAPortHandler: public MOS::MOS6522::IRQDelegatePortHandler {
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SystemVIAPortHandler(Audio &audio) : audio_(audio) {}
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@@ -124,6 +135,213 @@ private:
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Audio &audio_;
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};
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/*!
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Handles CRTC bus activity.
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*/
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class CRTCBusHandler {
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public:
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CRTCBusHandler(const uint8_t *const ram) :
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crt_(1024, 1, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red1Green1Blue1),
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ram_(ram) {}
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void set_palette(const uint8_t value) {
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const auto index = value >> 4;
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Logger::info().append("Palette entry %d set to %x", index, value & 0xf);
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}
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void set_control(const uint8_t value) {
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Logger::info().append("Video control set to %x", value);
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}
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/*!
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The CRTC entry function for the main part of each clock cycle; takes the current
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bus state and determines what output to produce based on the current palette and mode.
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*/
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void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
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// // The gate array waits 2us to react to the CRTC's vsync signal, and then
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// // caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,
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// // respectively.
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// if(state.hsync) {
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// cycles_into_hsync_++;
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// } else {
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// cycles_into_hsync_ = 0;
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// }
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//
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// const bool is_hsync = (cycles_into_hsync_ >= 2 && cycles_into_hsync_ < 6);
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// const bool is_colour_burst = (cycles_into_hsync_ >= 7 && cycles_into_hsync_ < 11);
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//
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// // Sync is taken to override pixels, and is combined as a simple OR.
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// const bool is_sync = is_hsync || state.vsync;
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// const bool is_blank = !is_sync && state.hsync;
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//
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// OutputMode output_mode;
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// if(is_sync) {
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// output_mode = OutputMode::Sync;
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// } else if(is_colour_burst) {
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// output_mode = OutputMode::ColourBurst;
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// } else if(is_blank) {
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// output_mode = OutputMode::Blank;
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// } else if(state.display_enable) {
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// output_mode = OutputMode::Pixels;
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// } else {
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// output_mode = OutputMode::Border;
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// }
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//
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// // If a transition between sync/border/pixels just occurred, flush whatever was
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// // in progress to the CRT and reset counting.
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// if(output_mode != previous_output_mode_) {
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// if(cycles_) {
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// switch(previous_output_mode_) {
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// default:
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// case OutputMode::Blank: crt_.output_blank(cycles_ * 16); break;
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// case OutputMode::Sync: crt_.output_sync(cycles_ * 16); break;
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// case OutputMode::Border: output_border(cycles_); break;
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// case OutputMode::ColourBurst: crt_.output_default_colour_burst(cycles_ * 16); break;
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// case OutputMode::Pixels:
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// crt_.output_data(cycles_ * 16, size_t(cycles_ * 16 / pixel_divider_));
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// pixel_pointer_ = pixel_data_ = nullptr;
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// break;
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// }
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// }
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//
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// cycles_ = 0;
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// previous_output_mode_ = output_mode;
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// }
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//
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// // Increment cycles since state changed.
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// cycles_++;
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//
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// // Collect some more pixels if output is ongoing.
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// if(previous_output_mode_ == OutputMode::Pixels) {
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// if(!pixel_data_) {
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// pixel_pointer_ = pixel_data_ = crt_.begin_data(320, 8);
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// }
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// if(pixel_pointer_) {
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// // the CPC shuffles output lines as:
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// // MA13 MA12 RA2 RA1 RA0 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 CCLK
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// // ... so form the real access address.
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// const uint16_t address =
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// uint16_t(
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// ((state.refresh_address & 0x3ff) << 1) |
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// ((state.row_address & 0x7) << 11) |
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// ((state.refresh_address & 0x3000) << 2)
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// );
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//
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// // Fetch two bytes and translate into pixels. Guaranteed: the mode can change only at
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// // hsync, so there's no risk of pixel_pointer_ overrunning 320 output pixels without
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// // exactly reaching 320 output pixels.
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// switch(mode_) {
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// case 0:
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// reinterpret_cast<uint16_t *>(pixel_pointer_)[0] = mode0_output_[ram_[address]];
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// reinterpret_cast<uint16_t *>(pixel_pointer_)[1] = mode0_output_[ram_[address+1]];
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// pixel_pointer_ += 2 * sizeof(uint16_t);
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// break;
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//
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// case 1:
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// reinterpret_cast<uint32_t *>(pixel_pointer_)[0] = mode1_output_[ram_[address]];
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// reinterpret_cast<uint32_t *>(pixel_pointer_)[1] = mode1_output_[ram_[address+1]];
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// pixel_pointer_ += 2 * sizeof(uint32_t);
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// break;
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//
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// case 2:
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// reinterpret_cast<uint64_t *>(pixel_pointer_)[0] = mode2_output_[ram_[address]];
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// reinterpret_cast<uint64_t *>(pixel_pointer_)[1] = mode2_output_[ram_[address+1]];
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// pixel_pointer_ += 2 * sizeof(uint64_t);
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// break;
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//
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// case 3:
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// reinterpret_cast<uint16_t *>(pixel_pointer_)[0] = mode3_output_[ram_[address]];
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// reinterpret_cast<uint16_t *>(pixel_pointer_)[1] = mode3_output_[ram_[address+1]];
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// pixel_pointer_ += 2 * sizeof(uint16_t);
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// break;
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//
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// }
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//
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// // Flush the current buffer pixel if full; the CRTC allows many different display
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// // widths so it's not necessarily possible to predict the correct number in advance
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// // and using the upper bound could lead to inefficient behaviour.
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// if(pixel_pointer_ == pixel_data_ + 320) {
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// crt_.output_data(cycles_ * 16, size_t(cycles_ * 16 / pixel_divider_));
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// pixel_pointer_ = pixel_data_ = nullptr;
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// cycles_ = 0;
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// }
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// }
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// }
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//
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// // Latch mode four cycles after HSYNC was signalled, if still active.
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// if(cycles_into_hsync_ == 4 && mode_ != next_mode_) {
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// mode_ = next_mode_;
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// switch(mode_) {
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// default:
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// case 0: pixel_divider_ = 4; break;
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// case 1: pixel_divider_ = 2; break;
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// case 2: pixel_divider_ = 1; break;
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// }
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// build_mode_table();
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// }
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//
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// // For the interrupt timer: notify the leading edge of vertical sync and the
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// // trailing edge of horizontal sync.
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// if(was_vsync_ != state.vsync) {
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// interrupt_timer_.set_vsync(state.vsync);
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// }
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// if(was_hsync_ && !state.hsync) {
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// interrupt_timer_.signal_hsync();
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// }
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//
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// // Update current state for edge detection next time around.
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// was_vsync_ = state.vsync;
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// was_hsync_ = state.hsync;
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}
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/// Sets the destination for output.
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void set_scan_target(Outputs::Display::ScanTarget *const scan_target) {
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crt_.set_scan_target(scan_target);
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}
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/// @returns The current scan status.
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Outputs::Display::ScanStatus get_scaled_scan_status() const {
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return crt_.get_scaled_scan_status();
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}
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/// Sets the type of display.
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void set_display_type(const Outputs::Display::DisplayType display_type) {
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crt_.set_display_type(display_type);
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}
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/// Gets the type of display.
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Outputs::Display::DisplayType get_display_type() const {
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return crt_.get_display_type();
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}
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private:
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void output_border(const int length) {
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assert(length >= 0);
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crt_.output_blank(length * 16);
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}
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enum class OutputMode {
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Sync,
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Blank,
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ColourBurst,
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Border,
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Pixels
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} previous_output_mode_ = OutputMode::Sync;
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int cycles_ = 0;
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bool was_hsync_ = false, was_vsync_ = false;
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int cycles_into_hsync_ = 0;
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Outputs::CRT::CRT crt_;
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uint8_t *pixel_data_ = nullptr, *pixel_pointer_ = nullptr;
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const uint8_t *const ram_ = nullptr;
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};
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using CRTC = Motorola::CRTC::CRTC6845<
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CRTCBusHandler,
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Motorola::CRTC::Personality::HD6845S,
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Motorola::CRTC::CursorType::None>;
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}
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class ConcreteMachine:
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@@ -141,7 +359,9 @@ public:
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m6502_(*this),
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system_via_port_handler_(audio_),
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user_via_(user_via_port_handler_),
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system_via_(system_via_port_handler_)
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system_via_(system_via_port_handler_),
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crtc_bus_handler_(ram_.data()),
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crtc_(crtc_bus_handler_)
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{
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set_clock_rate(2'000'000);
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@@ -205,7 +425,7 @@ public:
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//
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// Dependent device updates.
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// 1Mhz devices.
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//
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const auto half_cycles = HalfCycles(duration.as_integral());
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audio_ += half_cycles;
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@@ -213,6 +433,12 @@ public:
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user_via_.run_for(half_cycles);
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//
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// 2Mhz devices.
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//
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// TODO: if CRTC clock is 1Mhz, adapt.
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crtc_.run_for(duration);
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//
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// Check for an IO access; if found then perform that and exit.
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//
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@@ -235,7 +461,37 @@ public:
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} else {
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page_sideways(*value & 0xf);
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}
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} else {
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} else if(address >= 0xfe00 && address < 0xfe08) {
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if(is_read(operation)) {
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if(address & 1) {
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*value = crtc_.get_register();
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} else {
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*value = crtc_.get_status();
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}
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} else {
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if(address & 1) {
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crtc_.set_register(*value);
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} else {
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crtc_.select_register(*value);
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}
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}
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} else if(address >= 0xfe20 && address < 0xfe30) {
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if(is_read(operation)) {
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*value = 0xfe;
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} else {
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switch(address) {
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case 0xfe20:
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crtc_bus_handler_.set_control(*value);
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crtc_2mhz_ = *value & 0x08;
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break;
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case 0xfe21:
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crtc_bus_handler_.set_palette(*value);
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break;
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}
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}
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}
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else {
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Logger::error()
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.append("Unhandled IO %s at %04x", is_read(operation) ? "read" : "write", address)
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.append_if(!is_read(operation), ": %02x", *value);
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@@ -269,9 +525,12 @@ private:
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}
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// MARK: - ScanProducer.
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void set_scan_target(Outputs::Display::ScanTarget *) override {}
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Outputs::Display::ScanStatus get_scan_status() const override {
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return Outputs::Display::ScanStatus{};
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void set_scan_target(Outputs::Display::ScanTarget *const target) override {
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crtc_bus_handler_.set_scan_target(target);
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return crtc_bus_handler_.get_scaled_scan_status();
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}
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// MARK: - TimedMachine.
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@@ -339,6 +598,10 @@ private:
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}
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Audio audio_;
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CRTCBusHandler crtc_bus_handler_;
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CRTC crtc_;
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bool crtc_2mhz_ = true;
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};
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}
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