diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp
index f067b82f7..d583272b6 100644
--- a/InstructionSets/PowerPC/Instruction.hpp
+++ b/InstructionSets/PowerPC/Instruction.hpp
@@ -120,8 +120,9 @@ enum class Operation: uint8_t {
 
 	/// Branch conditional.
 	///
+	/// aa() determines whether the branch has a relative or absolute target.
 	/// lk() determines whether to update the link register.
-	/// bd() supplies a relative displacment.
+	/// bd() supplies a relative displacment or absolute address.
 	/// bi() specifies which CR bit to use as a condition; cf. the Condition enum.
 	/// bo() provides other branch options and a branch prediction hint as per (BranchOptions enum << 1) | hint.
 	///
@@ -131,7 +132,7 @@ enum class Operation: uint8_t {
 
 	/// Branch conditional to count register.
 	///
-	/// bi(), bo() and lk() are as per bcx.
+	/// aa(), bi(), bo() and lk() are as per bcx.
 	///
 	/// On the MPC601, anything that decrements the count register will use the non-decremented
 	/// version as the branch target. Other processors will use the decremented version.
@@ -139,7 +140,7 @@ enum class Operation: uint8_t {
 
 	/// Branch conditional to link register.
 	///
-	/// bi(), bo() and lk() are as per bcx.
+	/// aa(), bi(), bo() and lk() are as per bcx.
 	bclrx,
 
 	cmp, cmpi, cmpl, cmpli,
diff --git a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm
index b1b5b90bb..b5f2b6aef 100644
--- a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm	
@@ -116,14 +116,14 @@ using namespace InstructionSet::PowerPC;
 					break;
 
 					case Operation::bcx: {
-//						if(instruction.aa()) {
-//							baseOperation = [baseOperation stringByAppendingString:@"a"];
-//						} else {
-//
-//						}
+						uint32_t decoded_destination;
+						if(instruction.aa()) {
+							decoded_destination = instruction.bd();
+						} else {
+							decoded_destination = instruction.bd() + address;
+						}
 
 						const uint32_t destination = uint32_t(std::strtol([[columns lastObject] UTF8String], 0, 16));
-						const uint32_t decoded_destination = instruction.bd() + address;
 						XCTAssertEqual(decoded_destination, destination);
 					} break;
 
@@ -136,6 +136,9 @@ using namespace InstructionSet::PowerPC;
 					if(instruction.lk()) {
 						baseOperation = [baseOperation stringByAppendingString:@"l"];
 					}
+					if(instruction.aa()) {
+						baseOperation = [baseOperation stringByAppendingString:@"a"];
+					}
 					if(instruction.branch_prediction_hint()) {
 						baseOperation = [baseOperation stringByAppendingString:@"+"];
 					}