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Completely bypass ignored tests.

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This commit is contained in:
Thomas Harte 2024-03-28 11:28:37 -04:00
parent 2e7c1acb88
commit 740b0e35d5
1 changed files with 10 additions and 11 deletions
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21
OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm
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@ -377,7 +377,7 @@ struct MemoryLedger {
std::map<uint32_t, FailureRecord> failures; std::map<uint32_t, FailureRecord> failures;
uint32_t opcode = 0; uint32_t opcode = 0;
bool ignore_test = false; bool ignore_opcode = false;
uint32_t masks[16]; uint32_t masks[16];
uint32_t test_pc_offset = 8; uint32_t test_pc_offset = 8;
@ -388,7 +388,7 @@ struct MemoryLedger {
if(label == "**") { if(label == "**") {
memset(masks, 0xff, sizeof(masks)); memset(masks, 0xff, sizeof(masks));
ignore_test = false; ignore_opcode = false;
test_pc_offset = 8; test_pc_offset = 8;
input >> opcode; input >> opcode;
@ -413,7 +413,7 @@ struct MemoryLedger {
// Tested CPU either doesn't switch into supervisor mode, or // Tested CPU either doesn't switch into supervisor mode, or
// is sufficiently accurate in its pipeline that register // is sufficiently accurate in its pipeline that register
// changes haven't happened yet. // changes haven't happened yet.
ignore_test = true; ignore_opcode = true;
break; break;
case Instruction::Operation::MOV: case Instruction::Operation::MOV:
@ -428,7 +428,7 @@ struct MemoryLedger {
// MOV to PC; there are both pipeline capture errors in the test // MOV to PC; there are both pipeline capture errors in the test
// set and its ARM won't change privilege level on a write to R15. // set and its ARM won't change privilege level on a write to R15.
if(instruction.destination.value == 15) { if(instruction.destination.value == 15) {
ignore_test = true; ignore_opcode = true;
} }
break; break;
@ -442,20 +442,20 @@ struct MemoryLedger {
// doesn't seem to have that effect on the ARM used to generate // doesn't seem to have that effect on the ARM used to generate
// the test set. // the test set.
if(instruction.destination.value == 15 || instruction.operand2.value == 15) { if(instruction.destination.value == 15 || instruction.operand2.value == 15) {
ignore_test = true; ignore_opcode = true;
} }
break; break;
case Instruction::Operation::STM: case Instruction::Operation::STM:
case Instruction::Operation::LDM: case Instruction::Operation::LDM:
// If the PC is involved, just skip the test; PC/PSR differences abound. // If the PC is involved, just skip the test; PC/PSR differences abound.
ignore_test = instruction.operand1.value & (1 << 15); ignore_opcode = instruction.operand1.value & (1 << 15);
break; break;
case Instruction::Operation::MCR: case Instruction::Operation::MCR:
case Instruction::Operation::MRC: case Instruction::Operation::MRC:
// The test case doesn't seem to throw on a missing coprocessor. // The test case doesn't seem to throw on a missing coprocessor.
ignore_test = true; ignore_opcode = true;
break; break;
default: break; default: break;
@ -464,6 +464,8 @@ struct MemoryLedger {
continue; continue;
} }
if(ignore_opcode) continue;
if(label == "Before:" || label == "After:") { if(label == "Before:" || label == "After:") {
// Read register state. // Read register state.
uint32_t regs[16]; uint32_t regs[16];
@ -501,11 +503,8 @@ struct MemoryLedger {
} else { } else {
// Execute test and compare. // Execute test and compare.
++test_count; ++test_count;
if(ignore_test) {
continue;
}
if(opcode == 0xe5abb010 && test_count == 1) { if(opcode == 0xe892000b && test_count == 1) {
printf(""); printf("");
} }