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https://github.com/TomHarte/CLK.git
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The port input/output flags are now honoured; reading a port that is set as an output returns the current output value.
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@ -226,7 +226,11 @@ uint8_t AY38910::get_register_value() {
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0xe0, 0xe0, 0xe0, 0x00, 0x00, 0xf0, 0x00, 0x00
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};
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return registers_[selected_register_] | register_masks[selected_register_];
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switch(selected_register_) {
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default: return registers_[selected_register_] | register_masks[selected_register_];
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case 14: return (registers_[0x7] & 0x40) ? registers_[14] : port_inputs_[0];
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case 15: return (registers_[0x7] & 0x80) ? registers_[15] : port_inputs_[1];
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}
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}
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#pragma mark - Port handling
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@ -236,7 +240,7 @@ uint8_t AY38910::get_port_output(bool port_b) {
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}
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void AY38910::set_port_input(bool port_b, uint8_t value) {
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registers_[port_b ? 15 : 14] = value;
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port_inputs_[port_b ? 1 : 0] = value;
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update_bus();
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}
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@ -59,6 +59,7 @@ class AY38910: public ::Outputs::Filter<AY38910> {
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private:
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int selected_register_;
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uint8_t registers_[16], output_registers_[16];
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uint8_t port_inputs_[2];
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int master_divider_;
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