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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-07 08:28:57 +00:00

Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps.

This commit is contained in:
Thomas Harte 2016-07-11 22:12:58 -04:00
parent d0200b6fd9
commit 75d95c0bc0
3 changed files with 69 additions and 0 deletions

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@ -0,0 +1,9 @@
//
// DigitalPhaseLockedLoop.cpp
// Clock Signal
//
// Created by Thomas Harte on 11/07/2016.
// Copyright © 2016 Thomas Harte. All rights reserved.
//
#include "DigitalPhaseLockedLoop.hpp"

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@ -0,0 +1,54 @@
//
// DigitalPhaseLockedLoop.hpp
// Clock Signal
//
// Created by Thomas Harte on 11/07/2016.
// Copyright © 2016 Thomas Harte. All rights reserved.
//
#ifndef DigitalPhaseLockedLoop_hpp
#define DigitalPhaseLockedLoop_hpp
namespace Storage {
class DigitalPhaseLockedLoop {
public:
/*!
Instantiates a @c DigitalPhaseLockedLoop.
@param clocks_per_bit The expected number of cycles between each bit of input.
@param tolerance The maximum tolerance for bit windows extremes will be clocks_per_bit ± tolerance.
*/
DigitalPhaseLockedLoop(unsigned int clocks_per_bit, unsigned int tolerance);
/*!
Runs the loop, impliedly posting no pulses during that period.
@c number_of_cycles The time to run the loop for.
*/
void run_for_cycles(unsigned int number_of_cycles);
/*!
Announces a pulse at the current time.
*/
void add_pulse();
/*!
A receiver for PCM output data; called upon every recognised bit.
*/
class Delegate {
public:
virtual void digital_phase_locked_loop_output_bit(bool value) = 0;
};
void set_delegate(Delegate *delegate)
{
_delegate = delegate;
}
private:
Delegate *_delegate;
};
}
#endif /* DigitalPhaseLockedLoop_hpp */