From 704737144a13093aadfadb525c530049c1ca03d9 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sun, 18 Apr 2021 18:40:44 -0400 Subject: [PATCH 1/2] Corrects all interrupt timing for sign and off-by-one errors. --- Machines/Sinclair/ZXSpectrum/Video.hpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Machines/Sinclair/ZXSpectrum/Video.hpp b/Machines/Sinclair/ZXSpectrum/Video.hpp index 57f1996e9..246445f4d 100644 --- a/Machines/Sinclair/ZXSpectrum/Video.hpp +++ b/Machines/Sinclair/ZXSpectrum/Video.hpp @@ -98,7 +98,7 @@ template class Video { .contention_duration = 129 * 2, // i.e. interrupt is first signalled 14368 cycles before the first video fetch. - .interrupt_time = (228*311 - 14360) * 2, + .interrupt_time = (1 + 228*311 - 14365 - 5) * 2, .delays = { // Should start at 14365 2, 1, @@ -123,7 +123,7 @@ template class Video { .contention_leadin = 4 * 2, .contention_duration = 128 * 2, - .interrupt_time = (228*311 - 14357) * 2, + .interrupt_time = (1 + 228*311 - 14361 - 4) * 2, .delays = { // Should start at 14361. 12, 11, @@ -148,7 +148,7 @@ template class Video { .contention_leadin = 4 * 2, .contention_duration = 128 * 2, - .interrupt_time = (224*312 - 14331) * 2, + .interrupt_time = (1 + 224*312 - 14335 - 4) * 2, .delays = { // Should start at 14335. 12, 11, From 7bac18bd65695ed883d72e3bf82a7dea9c534fc6 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sun, 18 Apr 2021 18:41:24 -0400 Subject: [PATCH 2/2] Address bus load time is not + 1/2. --- Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp b/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp index cc7e28cac..30686b1f5 100644 --- a/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp +++ b/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp @@ -245,7 +245,7 @@ template class ConcreteMachine: // always occurs if it is in the $4000–$8000 range regardless of current // memory mapping. HalfCycles delay; - HalfCycles time = video_.time_since_flush() + HalfCycles(1); + HalfCycles time = video_.time_since_flush(); if((address & 0xc000) == 0x4000) { for(int c = 0; c < ((address & 1) ? 4 : 2); c++) { @@ -269,7 +269,7 @@ template class ConcreteMachine: // These all start by loading the address bus, then set MREQ // half a cycle later. if(is_contended_[address >> 14]) { - const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1)); + const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush()); advance(cycle.length + delay); return delay; @@ -284,7 +284,7 @@ template class ConcreteMachine: const auto half_cycles = cycle.length.as(); assert(!(half_cycles & 1)); - HalfCycles time = video_.time_since_flush() + HalfCycles(1); + HalfCycles time = video_.time_since_flush(); HalfCycles delay; for(int c = 0; c < half_cycles; c += 2) { const auto next_delay = video_.last_valid()->access_delay(time);