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https://github.com/TomHarte/CLK.git
synced 2025-11-01 11:16:16 +00:00
Install extra cycle for 65c02 decimal arithmetic.
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@@ -86,7 +86,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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default:
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__builtin_unreachable();
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// MARK: - Read, write or modify accesses.
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// MARK: - Read, write or modify a zero-page address.
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access_zero:
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++registers.pc.full;
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@@ -100,6 +100,18 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto access_zero_write;
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}
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// ADC and SBC decimal take an extra cycle on the 65c02.
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if constexpr (is_65c02(model)) {
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if(
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(
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Storage::decoded_.operation == Operation::ADC ||
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Storage::decoded_.operation == Operation::SBC
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) && registers.flags.decimal
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) {
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goto access_zero_65c02_decimal;
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}
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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@@ -123,6 +135,15 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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access_zero_65c02_decimal:
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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// MARK: - Read, write or modify an arbitrary address.
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access_absolute:
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++registers.pc.full;
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if constexpr (is_65c02(model)) {
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@@ -134,6 +155,18 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto access_absolute_write;
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}
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// ADC and SBC decimal take an extra cycle on the 65c02.
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if constexpr (is_65c02(model)) {
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if(
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(
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Storage::decoded_.operation == Operation::ADC ||
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Storage::decoded_.operation == Operation::SBC
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) && registers.flags.decimal
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) {
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goto access_absolute_65c02_decimal;
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}
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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@@ -157,6 +190,13 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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access_absolute_65c02_decimal:
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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// MARK: - Fetch/decode.
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fetch_decode:
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@@ -172,9 +212,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto interrupt;
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}
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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access(BusOperation::ReadOpcode, Literal(registers.pc.full), Storage::opcode_);
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++registers.pc.full;
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Storage::decoded_ = Decoder<model>::decode(Storage::opcode_);
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