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Install extra cycle for 65c02 decimal arithmetic.

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This commit is contained in:
Thomas Harte
2025-10-24 21:24:05 -04:00
parent 0d72c75e15
commit 76a5872d17
1 changed files with 41 additions and 4 deletions
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45
Processors/6502Mk2/Implementation/6502.hpp
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@@ -86,7 +86,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
default: default:
__builtin_unreachable(); __builtin_unreachable();
// MARK: - Read, write or modify accesses. // MARK: - Read, write or modify a zero-page address.
access_zero: access_zero:
++registers.pc.full; ++registers.pc.full;
@@ -100,6 +100,18 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
goto access_zero_write; goto access_zero_write;
} }
// ADC and SBC decimal take an extra cycle on the 65c02.
if constexpr (is_65c02(model)) {
if(
(
Storage::decoded_.operation == Operation::ADC ||
Storage::decoded_.operation == Operation::SBC
) && registers.flags.decimal
) {
goto access_zero_65c02_decimal;
}
}
// Read. // Read.
check_interrupt(); check_interrupt();
access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_); access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
@@ -123,6 +135,15 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
goto fetch_decode; goto fetch_decode;
access_zero_65c02_decimal:
access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
check_interrupt();
access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
perform_operation();
goto fetch_decode;
// MARK: - Read, write or modify an arbitrary address.
access_absolute: access_absolute:
++registers.pc.full; ++registers.pc.full;
if constexpr (is_65c02(model)) { if constexpr (is_65c02(model)) {
@@ -134,6 +155,18 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
goto access_absolute_write; goto access_absolute_write;
} }
// ADC and SBC decimal take an extra cycle on the 65c02.
if constexpr (is_65c02(model)) {
if(
(
Storage::decoded_.operation == Operation::ADC ||
Storage::decoded_.operation == Operation::SBC
) && registers.flags.decimal
) {
goto access_absolute_65c02_decimal;
}
}
// Read. // Read.
check_interrupt(); check_interrupt();
access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_); access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
@@ -157,6 +190,13 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
goto fetch_decode; goto fetch_decode;
access_absolute_65c02_decimal:
access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
check_interrupt();
perform_operation();
access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
goto fetch_decode;
// MARK: - Fetch/decode. // MARK: - Fetch/decode.
fetch_decode: fetch_decode:
@@ -172,9 +212,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
goto interrupt; goto interrupt;
} }
if constexpr (is_65c02(model)) {
check_interrupt();
}
access(BusOperation::ReadOpcode, Literal(registers.pc.full), Storage::opcode_); access(BusOperation::ReadOpcode, Literal(registers.pc.full), Storage::opcode_);
++registers.pc.full; ++registers.pc.full;
Storage::decoded_ = Decoder<model>::decode(Storage::opcode_); Storage::decoded_ = Decoder<model>::decode(Storage::opcode_);