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Corrects PEA and adds an additional debugging aid.
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@ -261,6 +261,13 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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#endif
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#endif
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decoded_instruction_.full = prefetch_queue_.halves.high.full;
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decoded_instruction_.full = prefetch_queue_.halves.high.full;
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#ifndef NDEBUG
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/* Debugging feature: reset the effective addresses and data latches, so that it's
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more obvious if some of the instructions aren't properly feeding them. */
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effective_address_[0].full = effective_address_[1].full = source_bus_data_[0].full = destination_bus_data_[0].full = 0x12344321;
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#endif
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#ifdef LOG_TRACE
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#ifdef LOG_TRACE
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if(should_log) {
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if(should_log) {
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std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_.full << '\t';
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std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_.full << '\t';
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@ -272,7 +279,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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}
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}
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#ifdef LOG_TRACE
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#ifdef LOG_TRACE
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should_log |= ((program_counter_.full - 4) == 0x40103e);
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should_log |= ((program_counter_.full - 4) == 0x4058dc); // 0x40103e
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#endif
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#endif
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if(instructions[decoded_instruction_.full].micro_operations) {
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if(instructions[decoded_instruction_.full].micro_operations) {
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@ -2407,6 +2407,7 @@ struct ProcessorStorageConstructor {
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case XXXl: // PEA (XXX).l
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case XXXl: // PEA (XXX).l
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case XXXw: // PEA (XXX).w
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case XXXw: // PEA (XXX).w
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storage_.instructions[instruction].source = &storage_.effective_address_[0];
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
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op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
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op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
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@ -2416,6 +2417,7 @@ struct ProcessorStorageConstructor {
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case d16PC: // PEA (d16, PC)
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case d16PC: // PEA (d16, PC)
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case d8AnXn: // PEA (d8, An, Xn)
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case d8AnXn: // PEA (d8, An, Xn)
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case d8PCXn: // PEA (d8, PC, Xn)
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case d8PCXn: // PEA (d8, PC, Xn)
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storage_.instructions[instruction].source = &storage_.effective_address_[0];
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
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op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));
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op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));
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