mirror of
https://github.com/TomHarte/CLK.git
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Evict MOVEM and MOVEP, enable TRAP and TRAPV, complete CHK.
This commit is contained in:
Thomas Harte
parent
cde75a1c00
commit
78b60dbd1a
@ -435,10 +435,9 @@ template <
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// JMP: copies EA(0) to the program counter.
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// case Operation::JMP:
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// program_counter_ = effective_address_[0];
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// flow_controller.set_pc(effective_address_[0]);
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// break;
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// JMP: copies the source bus data to the program counter.
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// case Operation::RTS:
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// program_counter_ = source_bus_data_;
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// break;
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@ -701,208 +700,16 @@ template <
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#undef announce_divide_by_zero
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/*
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MOVEP: move words and long-words a byte at a time.
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*/
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// case Operation::MOVEPtoMw:
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// // Write pattern is nW+ nw, which should write the low word of the source in big-endian form.
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// destination_bus_data_.halves.high.l = src.halves.low.halves.high;
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// destination_bus_data_.w = src.b;
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// break;
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//
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// case Operation::MOVEPtoMl:
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// // Write pattern is nW+ nWr+ nw+ nwr, which should write the source in big-endian form.
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// destination_bus_data_.halves.high.l = src.halves.high.halves.high;
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// source_bus_data_.halves.high.l = src.halves.high.halves.low;
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// destination_bus_data_.w = src.halves.low.halves.high;
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// source_bus_data_.w = src.b;
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// break;
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//
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// case Operation::MOVEPtoRw:
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// // Read pattern is nRd+ nrd.
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// src.halves.low.halves.high = destination_bus_data_.halves.high.halves.low;
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// src.b = destination_bus_data_.b;
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// break;
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//
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// case Operation::MOVEPtoRl:
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// // Read pattern is nRd+ nR+ nrd+ nr.
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// src.halves.high.halves.high = destination_bus_data_.halves.high.halves.low;
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// src.halves.high.halves.low = source_bus_data_.halves.high.halves.low;
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// src.halves.low.halves.high = destination_bus_data_.b;
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// src.b = source_bus_data_.b;
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// break;
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/*
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MOVEM: multi-word moves.
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*/
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//#define setup_movem(words_per_reg, base) \
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// /* Count the number of long words to move. */ \
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// size_t total_to_move = 0; \
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// auto mask = next_word_; \
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// while(mask) { \
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// total_to_move += mask&1; \
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// mask >>= 1; \
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// } \
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// \
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// /* Twice that many words plus one will need to be moved */ \
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// bus_program = base + (64 - total_to_move*words_per_reg)*2; \
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// \
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// /* Fill in the proper addresses and targets. */ \
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// const auto mode = (decoded_instruction_.l >> 3) & 7; \
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// uint32_t start_address; \
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// if(mode <= 4) { \
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// start_address = destination_address().l; \
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// } else { \
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// start_address = effective_address_[1].l; \
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// } \
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// \
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//auto step = bus_program; \
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//uint32_t *address_storage = precomputed_addresses_; \
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//mask = next_word_; \
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//int offset = 0;
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//
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//#define inc_action(x, v) x += v
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//#define dec_action(x, v) x -= v
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//
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//#define write_address_sequence_long(action, l) \
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//while(mask) { \
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//if(mask&1) { \
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//address_storage[0] = start_address; \
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//action(start_address, 2); \
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//address_storage[1] = start_address; \
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//action(start_address, 2); \
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// \
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//step[0].microcycle.address = step[1].microcycle.address = address_storage; \
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//step[2].microcycle.address = step[3].microcycle.address = address_storage + 1; \
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// \
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//const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset]; \
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//step[l].microcycle.value = step[l+1].microcycle.value = &target->halves.high; \
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//step[(l^2)].microcycle.value = step[(l^2)+1].microcycle.value = &target->halves.low; \
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// \
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//address_storage += 2; \
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//step += 4; \
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//} \
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//mask >>= 1; \
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//action(offset, 1); \
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//}
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//
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//#define write_address_sequence_word(action) \
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//while(mask) { \
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//if(mask&1) { \
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//address_storage[0] = start_address; \
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//action(start_address, 2); \
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// \
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//step[0].microcycle.address = step[1].microcycle.address = address_storage; \
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// \
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//const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset]; \
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//step[0].microcycle.value = step[1].microcycle.value = &target->halves.low; \
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// \
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//++ address_storage; \
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//step += 2; \
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//} \
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//mask >>= 1; \
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//action(offset, 1); \
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//}
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//
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// case Operation::MOVEMtoRl: {
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// setup_movem(2, movem_read_steps_);
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//
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// // Everything for move to registers is based on an incrementing
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// // address; per M68000PRM:
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// //
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// // "[If using the postincrement addressing mode then] the incremented address
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// // register contains the address of the last operand loaded plus the operand length.
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// // If the addressing register is also loaded from memory, the memory value is ignored
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// // and the register is written with the postincremented effective address."
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// //
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// // The latter part is dealt with by MicroOp::Action::MOVEMtoRComplete, which also
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// // does any necessary sign extension.
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// write_address_sequence_long(inc_action, 0);
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//
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// // MOVEM to R always reads one word too many.
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// address_storage[0] = start_address;
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// step[0].microcycle.address = step[1].microcycle.address = address_storage;
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// step[0].microcycle.value = step[1].microcycle.value = &throwaway_value_;
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// movem_final_address_ = start_address;
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// } break;
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//
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// case Operation::MOVEMtoRw: {
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// setup_movem(1, movem_read_steps_);
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// write_address_sequence_word(inc_action);
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//
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// // MOVEM to R always reads one word too many.
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// address_storage[0] = start_address;
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// step[0].microcycle.address = step[1].microcycle.address = address_storage;
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// step[0].microcycle.value = step[1].microcycle.value = &throwaway_value_;
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// movem_final_address_ = start_address;
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// } break;
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//
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// case Operation::MOVEMtoMl: {
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// setup_movem(2, movem_write_steps_);
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//
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// // MOVEM to M counts downwards and enumerates the registers in reverse order
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// // if subject to the predecrementing mode; otherwise it counts upwards and
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// // operates exactly as does MOVEM to R.
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// //
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// // Note also: "The MC68000 and MC68010 write the initial register value
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// // (not decremented) [when writing a register that is providing
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// // pre-decrementing addressing]."
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// //
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// // Hence the decrementing register (if any) is updated
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// // by MicroOp::Action::MOVEMtoMComplete.
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// if(mode == 4) {
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// offset = 15;
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// start_address -= 2;
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// write_address_sequence_long(dec_action, 2);
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// movem_final_address_ = start_address + 2;
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// } else {
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// write_address_sequence_long(inc_action, 0);
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// }
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// } break;
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//
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// case Operation::MOVEMtoMw: {
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// setup_movem(1, movem_write_steps_);
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//
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// if(mode == 4) {
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// offset = 15;
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// start_address -= 2;
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// write_address_sequence_word(dec_action);
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// movem_final_address_ = start_address + 2;
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// } else {
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// write_address_sequence_word(inc_action);
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// }
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// } break;
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//
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//#undef setup_movem
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//#undef write_address_sequence_long
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//#undef write_address_sequence_word
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//#undef inc_action
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//#undef dec_action
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// TRAP, which is a nicer form of ILLEGAL.
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// case Operation::TRAP: {
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// Select the trap steps as next; the initial microcycle should be 4 cycles long.
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// bus_program = trap_steps_;
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// populate_trap_steps((decoded_instruction_.l & 15) + 32, status());
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// set_next_microcycle_length(HalfCycles(12));
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case Operation::TRAP:
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flow_controller.raise_exception(src.l + 32);
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break;
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// The program counter to push is actually one slot ago.
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// program_counter_.l -= 2;
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// } break;
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// case Operation::TRAPV: {
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// if(overflow_flag_) {
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// // Select the trap steps as next; the initial microcycle should be skipped.
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// bus_program = trap_steps_;
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// populate_trap_steps(7, status());
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// set_next_microcycle_length(HalfCycles(4));
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//
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// // Push the address after the TRAPV.
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// program_counter_.l -= 4;
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// }
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// } break;
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case Operation::TRAPV: {
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if(status.overflow_flag_) {
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flow_controller.raise_exception(7);
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}
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} break;
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case Operation::CHK: {
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const bool is_under = s_extend16(dest.w) < 0;
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@ -915,25 +722,18 @@ template <
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//
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// if Dn < 0, set negative flag;
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// otherwise, if Dn > <ea>, reset negative flag.
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if(is_over) status.negative_flag_ = 0;
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if(is_under) status.negative_flag_ = 1;
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if(is_over) status.negative_flag_ = 0;
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if(is_under) status.negative_flag_ = 1;
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// No exception is the default course of action; deviate only if an
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// exception is necessary.
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if(is_under || is_over) {
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// bus_program = trap_steps_;
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// populate_trap_steps(6, status());
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// if(is_over) {
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// set_next_microcycle_length(HalfCycles(20));
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// } else {
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// set_next_microcycle_length(HalfCycles(24));
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// }
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// The program counter to push is two slots ago as whatever was the correct prefetch
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// to continue without an exception has already happened, just in case.
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// program_counter_.l -= 4;
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assert(false);
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// TODO.
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if(is_over) {
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flow_controller.consume_cycles(10);
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} else {
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flow_controller.consume_cycles(12);
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}
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flow_controller.raise_exception(6);
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}
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} break;
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@ -1045,7 +845,7 @@ template <
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// src.l = address_[7].l;
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// address_[7].l += u_extend16(prefetch_queue_.w);
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// break;
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//
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// case Operation::UNLINK:
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// address_[7].l = effective_address_[1].l + 2;
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// dest.l = destination_bus_data_.l;
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@ -1223,8 +1023,8 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::ASLb: asl(dest.b, 8); break;
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// case Operation::ASLw: asl(dest.w, 16); break;
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// case Operation::ASLl: asl(dest.l, 32); break;
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// case Operation::ASLw: asl(dest.w, 16); break;
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// case Operation::ASLl: asl(dest.l, 32); break;
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#define asr(destination, size) {\
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decode_shift_count(); \
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@ -1254,8 +1054,8 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::ASRb: asr(dest.b, 8); break;
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// case Operation::ASRw: asr(dest.w, 16); break;
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// case Operation::ASRl: asr(dest.l, 32); break;
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// case Operation::ASRw: asr(dest.w, 16); break;
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// case Operation::ASRl: asr(dest.l, 32); break;
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#undef set_neg_zero_overflow
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@ -1291,8 +1091,8 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::LSLb: lsl(dest.b, 8); break;
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// case Operation::LSLw: lsl(dest.w, 16); break;
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// case Operation::LSLl: lsl(dest.l, 32); break;
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// case Operation::LSLw: lsl(dest.w, 16); break;
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// case Operation::LSLl: lsl(dest.l, 32); break;
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#define lsr(destination, size) {\
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decode_shift_count(); \
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@ -1315,8 +1115,8 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::LSRb: lsr(dest.b, 8); break;
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// case Operation::LSRw: lsr(dest.w, 16); break;
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// case Operation::LSRl: lsr(dest.l, 32); break;
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// case Operation::LSRw: lsr(dest.w, 16); break;
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// case Operation::LSRl: lsr(dest.l, 32); break;
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#define rol(destination, size) { \
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decode_shift_count(); \
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@ -1343,8 +1143,8 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::ROLb: rol(dest.b, 8); break;
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// case Operation::ROLw: rol(dest.w, 16); break;
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// case Operation::ROLl: rol(dest.l, 32); break;
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// case Operation::ROLw: rol(dest.w, 16); break;
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// case Operation::ROLl: rol(dest.l, 32); break;
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#define ror(destination, size) { \
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decode_shift_count(); \
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@ -1371,12 +1171,10 @@ template <
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set_neg_zero_overflow(dest.w, 0x8000);
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} break;
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// case Operation::RORb: ror(dest.b, 8); break;
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// case Operation::RORw: ror(dest.w, 16); break;
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// case Operation::RORl: ror(dest.l, 32); break;
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// case Operation::RORw: ror(dest.w, 16); break;
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// case Operation::RORl: ror(dest.l, 32); break;
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#define roxl(destination, size) { \
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decode_shift_count(); \
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\
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shift_count %= (size + 1); \
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uint64_t compound = uint64_t(destination) | (status.extend_flag_ ? (1ull << size) : 0); \
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compound = \
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@ -1394,9 +1192,9 @@ template <
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status.extend_flag_ = value & 0x8000;
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set_flags_w(0x8000);
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} break;
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// case Operation::ROXLb: roxl(dest.b, 8); break;
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// case Operation::ROXLw: roxl(dest.w, 16); break;
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// case Operation::ROXLl: roxl(dest.l, 32); break;
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// case Operation::ROXLb: roxl(dest.b, 8); break;
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// case Operation::ROXLw: roxl(dest.w, 16); break;
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// case Operation::ROXLl: roxl(dest.l, 32); break;
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#define roxr(destination, size) { \
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decode_shift_count(); \
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@ -1418,9 +1216,9 @@ template <
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status.extend_flag_ = value & 0x0001;
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set_flags_w(0x0001);
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} break;
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// case Operation::ROXRb: roxr(dest.b, 8); break;
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// case Operation::ROXRw: roxr(dest.w, 16); break;
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// case Operation::ROXRl: roxr(dest.l, 32); break;
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// case Operation::ROXRb: roxr(dest.b, 8); break;
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// case Operation::ROXRw: roxr(dest.w, 16); break;
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// case Operation::ROXRl: roxr(dest.l, 32); break;
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#undef roxr
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#undef roxl
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@ -1474,10 +1272,10 @@ template <
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status.negative_flag_ = status.zero_result_ & 0x80000000;
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break;
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// case Operation::STOP:
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// apply_status(prefetch_queue_.w);
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// execution_state_ = ExecutionState::Stopped;
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// break;
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case Operation::STOP:
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status.set_status(src.w);
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flow_controller.stop();
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break;
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/*
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Development period debugging.
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