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Implements PEA.
This decreases the unimplemented count by 28 from 11841 to 11813.
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@ -456,6 +456,8 @@ struct ProcessorStorageConstructor {
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BCHG_BSET, // Maps a mode and register, and possibly a source register, to a BCHG or BSET.
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TAS, // Maps a mode and register to a TAS.
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PEA, // Maps a mode and register to a PEA.
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};
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using Operation = ProcessorStorage::Operation;
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@ -541,6 +543,8 @@ struct ProcessorStorageConstructor {
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{0xf000, 0x6000, Operation::Bcc, Decoder::Bcc_BSR}, // 4-25 (p129) and 4-59 (p163)
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{0xf1c0, 0x41c0, Operation::MOVEAl, Decoder::LEA}, // 4-110 (p214)
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{0xffc0, 0x4840, Operation::MOVEAl, Decoder::PEA}, // 4-159 (p263)
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{0xf100, 0x7000, Operation::MOVEq, Decoder::MOVEq}, // 4-134 (p238)
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{0xffff, 0x4e70, Operation::None, Decoder::RESET}, // 6-83 (p537)
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@ -2311,6 +2315,45 @@ struct ProcessorStorageConstructor {
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}
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} break;
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case Decoder::PEA: {
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const int mode = combined_mode(ea_mode, ea_register);
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storage_.instructions[instruction].source =
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(mode == Ind) ?
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&storage_.address_[ea_register] :
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&storage_.effective_address_[0];
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storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
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storage_.instructions[instruction].destination_address = &storage_.address_[7];
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// Common to all modes: decrement A7.
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op(int(Action::Decrement4) | MicroOp::DestinationMask);
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switch(mode) {
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default: continue;
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case Ind: // PEA (An)
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq("np nW+ nw", { ea(1), ea(1) }));
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break;
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case XXXl: // PEA (XXX).l
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case XXXw: // PEA (XXX).w
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
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op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
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break;
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case d16An: // PEA (d16, An)
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case d16PC: // PEA (d16, PC)
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case d8AnXn: // PEA (d8, An, Xn)
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case d8PCXn: // PEA (d8, PC, Xn)
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
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op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));
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break;
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}
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} break;
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case Decoder::LEA: {
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const int destination_register = (instruction >> 9) & 7;
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storage_.instructions[instruction].set_destination(storage_, An, destination_register);
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