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Consolidates different test port input selection.

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This commit is contained in:
Thomas Harte 2020-02-23 16:12:28 -05:00
parent 3f3229851b
commit 79dd402bc8
6 changed files with 48 additions and 9 deletions
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7
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.h
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@ -46,6 +46,11 @@ typedef NS_ENUM(NSInteger, CSTestMachineZ80Register) {
CSTestMachineZ80RegisterMemPtr
};
typedef NS_ENUM(NSInteger, CSTestMachinePortLogic) {
CSTestMachinePortLogicReturnUpperByte,
CSTestMachinePortLogicReturn191
};
@interface CSTestMachineZ80 : CSTestMachine
- (void)setData:(nonnull NSData *)data atAddress:(uint16_t)startAddress;
@ -67,4 +72,6 @@ typedef NS_ENUM(NSInteger, CSTestMachineZ80Register) {
@property(nonatomic) BOOL irqLine;
@property(nonatomic) BOOL waitLine;
@property(nonatomic) CSTestMachinePortLogic portLogic;
@end

24
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.mm
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@ -70,6 +70,16 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
}
}
#pragma mark - Port Logic
struct PortAccessDelegateTopByte: public CPU::Z80::AllRAMProcessor::PortAccessDelegate {
uint8_t z80_all_ram_processor_input(uint16_t port) final { return port >> 8; }
};
struct PortAccessDelegate191: public CPU::Z80::AllRAMProcessor::PortAccessDelegate {
uint8_t z80_all_ram_processor_input(uint16_t port) final { return 191; }
};
#pragma mark - Capture class
@interface CSTestMachineZ80BusOperationCapture()
@ -104,6 +114,9 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
NSMutableArray<CSTestMachineZ80BusOperationCapture *> *_busOperationCaptures;
int _timeSeekingReadOpcode;
PortAccessDelegateTopByte _topBytePortDelegate;
PortAccessDelegate191 _value191PortDelegate;
}
#pragma mark - Lifecycle
@ -114,6 +127,7 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
_processor->reset_power_on();
_busOperationHandler = new BusOperationHandler(self);
_busOperationCaptures = [[NSMutableArray alloc] init];
self.portLogic = CSTestMachinePortLogicReturnUpperByte;
}
return self;
}
@ -173,6 +187,16 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
_processor->set_wait_line(waitLine ? true : false);
}
- (void)setPortLogic:(CSTestMachinePortLogic)portLogic {
_portLogic = portLogic;
if(_portLogic == CSTestMachinePortLogicReturn191) {
_processor->set_port_access_delegate(&_value191PortDelegate);
} else {
_processor->set_port_access_delegate(&_topBytePortDelegate);
}
}
- (CPU::AllRAMProcessor *)processor {
return _processor;
}

1
OSBindings/Mac/Clock SignalTests/FUSETests.swift
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@ -176,6 +176,7 @@ class FUSETests: XCTestCase {
let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
let machine = CSTestMachineZ80()
machine.portLogic = .returnUpperByte
machine.captureBusActivity = true
initialState.set(onMachine: machine)

3
OSBindings/Mac/Clock SignalTests/PatrikRakTests.swift
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@ -31,6 +31,7 @@ class PatrikRakTests: XCTestCase, CSTestMachineTrapHandler {
// Create a machine.
let machine = CSTestMachineZ80()
machine.portLogic = .return191
// Copy everything from finalBlock+1 to the end of the file to $8000.
let fileContents = testData.subdata(in: finalBlock+1 ..< testData.count)
@ -90,7 +91,7 @@ class PatrikRakTests: XCTestCase, CSTestMachineTrapHandler {
func testMemptr() {
runTest("z80memptr")
// Result: 102 of 152 tests failed.
// Current status: 101 of 152 tests failed.
}
func testMachine(_ testMachine: CSTestMachine, didTrapAtAddress address: UInt16) {

8
Processors/Z80/AllRAM/Z80AllRAM.cpp
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@ -36,9 +36,7 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
case PartialMachineCycle::Output:
break;
case PartialMachineCycle::Input:
// This logic is selected specifically because it seems to match
// the FUSE unit tests. It might need factoring out.
*cycle.value = address >> 8;
*cycle.value = port_delegate_ ? port_delegate_->z80_all_ram_processor_input(address) : 0xff;
break;
case PartialMachineCycle::Internal:
@ -55,8 +53,8 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
break;
}
if(delegate_ != nullptr) {
delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
if(memory_delegate_ != nullptr) {
memory_delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
}
return HalfCycles(0);

14
Processors/Z80/AllRAM/Z80AllRAM.hpp
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@ -25,7 +25,14 @@ class AllRAMProcessor:
virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) = 0;
};
inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
delegate_ = delegate;
memory_delegate_ = delegate;
}
struct PortAccessDelegate {
virtual uint8_t z80_all_ram_processor_input(uint16_t port) { return 0xff; }
};
inline void set_port_access_delegate(PortAccessDelegate *delegate) {
port_delegate_ = delegate;
}
virtual void run_for(const Cycles cycles) = 0;
@ -39,8 +46,9 @@ class AllRAMProcessor:
virtual void set_wait_line(bool value) = 0;
protected:
MemoryAccessDelegate *delegate_;
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
MemoryAccessDelegate *memory_delegate_ = nullptr;
PortAccessDelegate *port_delegate_ = nullptr;
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
};
}