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Kicks the work of dealing with ASL/etc into the runtime.
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@ -918,6 +918,55 @@ struct ProcessorStorageConstructor {
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}
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} break;
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case Decoder::ASLRLSLRROLRROXLRr: {
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storage_.instructions[instruction].set_destination(storage_, 0, ea_register);
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// All decoding occurs at runtime.
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op(Action::PerformOperation);
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} break;
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case Decoder::ASLRLSLRROLRROXLRm: {
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storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
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switch(combined_mode(ea_mode, ea_register)) {
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default: continue;
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case 0x02: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (An)
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case 0x03: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (An)+
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op(Action::None, seq("nrd np", { a(ea_register) }));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }));
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if(ea_mode == 0x03) {
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op(int(Action::Increment2) | MicroOp::DestinationMask);
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}
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break;
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case 0x04: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w -(An)
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op(int(Action::Decrement2) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }));
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break;
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case 0x05: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (d16, An)
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case 0x06: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (d8, An, Xn)
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op( calc_action_for_mode(ea_mode) | MicroOp::DestinationMask,
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seq(pseq("np nrd np", ea_mode), { ea(1) }));
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op(Action::PerformOperation, seq("nw", { ea(1) }));
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break;
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case 0x10: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (xxx).w
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op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }));
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op(Action::PerformOperation, seq("nw", { ea(1) }));
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break;
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case 0x11: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (xxx).l
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op(Action::None, seq("np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }));
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op(Action::PerformOperation, seq("nw", { ea(1) }));
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break;
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}
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} break;
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case Decoder::CLRNEGNEGXNOT: {
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const bool is_byte_access = !!((instruction >> 6)&3);
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const bool is_long_word_access = ((instruction >> 6)&3) == 2;
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