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https://github.com/TomHarte/CLK.git
synced 2024-12-26 09:29:45 +00:00
Eliminates the fiction of setting and getting registers.
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
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c46007332a
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@ -39,11 +39,9 @@ void DiskII::set_control(Control control, bool on) {
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case Control::Motor:
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case Control::Motor:
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motor_is_enabled_ = on;
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motor_is_enabled_ = on;
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drives_[active_drive_].set_motor_on(on);
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drives_[active_drive_].set_motor_on(on);
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break;
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return;
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}
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}
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// printf("%0x: Set control %d %s\n", stepper_mask_, control, on ? "on" : "off");
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// If the stepper magnet selections have changed, and any is on, see how
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// If the stepper magnet selections have changed, and any is on, see how
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// that moves the head.
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// that moves the head.
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if(previous_stepper_mask ^ stepper_mask_ && stepper_mask_) {
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if(previous_stepper_mask ^ stepper_mask_ && stepper_mask_) {
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@ -63,14 +61,7 @@ void DiskII::set_control(Control control, bool on) {
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}
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}
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}
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}
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void DiskII::set_mode(Mode mode) {
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// printf("Set mode %d\n", mode);
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inputs_ = (inputs_ & ~input_mode) | ((mode == Mode::Write) ? input_mode : 0);
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set_controller_can_sleep();
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}
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void DiskII::select_drive(int drive) {
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void DiskII::select_drive(int drive) {
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// printf("Select drive %d\n", drive);
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if((drive&1) == active_drive_) return;
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if((drive&1) == active_drive_) return;
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drives_[active_drive_].set_event_delegate(this);
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drives_[active_drive_].set_event_delegate(this);
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@ -81,20 +72,6 @@ void DiskII::select_drive(int drive) {
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drives_[active_drive_].set_motor_on(motor_is_enabled_);
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drives_[active_drive_].set_motor_on(motor_is_enabled_);
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}
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}
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void DiskII::set_data_register(uint8_t value) {
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// printf("Set data register (?)\n");
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inputs_ |= input_command;
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shift_register_ = value;
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set_controller_can_sleep();
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}
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uint8_t DiskII::get_shift_register() {
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// if(shift_register_ & 0x80) printf("[%02x] ", shift_register_);
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inputs_ &= ~input_command;
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set_controller_can_sleep();
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return shift_register_;
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}
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void DiskII::run_for(const Cycles cycles) {
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void DiskII::run_for(const Cycles cycles) {
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if(is_sleeping()) return;
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if(is_sleeping()) return;
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@ -124,11 +101,7 @@ void DiskII::run_for(const Cycles cycles) {
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return;
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return;
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}
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}
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break;
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break;
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case 0xb:
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case 0xb: shift_register_ = data_input_; break; // load data register from data bus
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// load data register from data bus...
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printf("TODO\n");
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// shift_register_ = data_register_;
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break; // load
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}
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}
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// TODO: surely there's a less heavyweight solution than this?
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// TODO: surely there's a less heavyweight solution than this?
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@ -221,15 +194,11 @@ bool DiskII::is_sleeping() {
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return controller_can_sleep_ && drive_is_sleeping_[0] && drive_is_sleeping_[1];
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return controller_can_sleep_ && drive_is_sleeping_[0] && drive_is_sleeping_[1];
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}
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}
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void DiskII::set_register(int address, uint8_t value) {
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void DiskII::set_data_input(uint8_t input) {
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trigger_address(address, value);
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data_input_ = input;
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}
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}
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uint8_t DiskII::get_register(int address) {
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int DiskII::read_address(int address) {
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return trigger_address(address, 0xff);
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}
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uint8_t DiskII::trigger_address(int address, uint8_t value) {
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switch(address & 0xf) {
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switch(address & 0xf) {
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default:
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default:
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case 0x0: set_control(Control::P0, false); break;
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case 0x0: set_control(Control::P0, false); break;
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@ -241,22 +210,19 @@ uint8_t DiskII::trigger_address(int address, uint8_t value) {
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case 0x6: set_control(Control::P3, false); break;
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case 0x6: set_control(Control::P3, false); break;
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case 0x7: set_control(Control::P3, true); break;
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case 0x7: set_control(Control::P3, true); break;
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case 0x8: set_control(Control::Motor, false); break;
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case 0x8:
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shift_register_ = 0;
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set_control(Control::Motor, false);
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break;
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case 0x9: set_control(Control::Motor, true); break;
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case 0x9: set_control(Control::Motor, true); break;
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case 0xa: select_drive(0); break;
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case 0xa: select_drive(0); break;
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case 0xb: select_drive(1); break;
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case 0xb: select_drive(1); break;
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case 0xc:
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case 0xc: inputs_ &= ~input_command; break;
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inputs_ &= ~input_command;
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case 0xd: inputs_ |= input_command; break;
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break;
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case 0xe: inputs_ &= ~input_mode; break;
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case 0xd: set_data_register(value); break;
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case 0xf: inputs_ |= input_mode; break;
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case 0xe:
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set_mode(Mode::Read);
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break;
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// return shift_register_;
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case 0xf: set_mode(Mode::Write); break;
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}
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}
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set_controller_can_sleep();
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set_controller_can_sleep();
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return (address & 1) ? 0xff : shift_register_;
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return (address & 1) ? 0xff : shift_register_;
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@ -33,15 +33,48 @@ class DiskII:
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public:
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public:
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DiskII();
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DiskII();
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void set_register(int address, uint8_t value);
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/// Sets the current external value of the data bus.
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uint8_t get_register(int address);
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void set_data_input(uint8_t input);
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/*!
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Submits an access to address @c address.
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@returns The 8-bit value loaded to the data bus by the DiskII if any;
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@c DidNotLoad otherwise.
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*/
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int read_address(int address);
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/*!
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The value returned by @c read_address if accessing that address
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didn't cause the disk II to place anything onto the bus.
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*/
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const int DidNotLoad = -1;
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/// Advances the controller by @c cycles.
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void run_for(const Cycles cycles);
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void run_for(const Cycles cycles);
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/*!
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Supplies the image of the state machine (i.e. P6) ROM,
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which dictates how the Disk II will respond to input.
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To reduce processing costs, some assumptions are made by
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the implementation as to the content of this ROM.
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Including:
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If Q6 is set and Q7 is reset, the controller is testing
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for write protect. If and when the shift register has
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become full with the state of the write protect value,
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no further processing is required.
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*/
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void set_state_machine(const std::vector<uint8_t> &);
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void set_state_machine(const std::vector<uint8_t> &);
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/// Inserts @c disk into the drive @c drive.
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void set_disk(const std::shared_ptr<Storage::Disk::Disk> &disk, int drive);
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void set_disk(const std::shared_ptr<Storage::Disk::Disk> &disk, int drive);
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// As per Sleeper.
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bool is_sleeping() override;
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bool is_sleeping() override;
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// The Disk II functions as a potential target for @c Activity::Sources.
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void set_activity_observer(Activity::Observer *observer);
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void set_activity_observer(Activity::Observer *observer);
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private:
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private:
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@ -55,8 +88,6 @@ class DiskII:
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void set_control(Control control, bool on);
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void set_control(Control control, bool on);
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void set_mode(Mode mode);
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void set_mode(Mode mode);
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void select_drive(int drive);
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void select_drive(int drive);
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void set_data_register(uint8_t value);
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uint8_t get_shift_register();
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uint8_t trigger_address(int address, uint8_t value);
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uint8_t trigger_address(int address, uint8_t value);
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void process_event(const Storage::Disk::Track::Event &event) override;
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void process_event(const Storage::Disk::Track::Event &event) override;
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@ -78,6 +109,8 @@ class DiskII:
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bool motor_is_enabled_ = false;
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bool motor_is_enabled_ = false;
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void set_controller_can_sleep();
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void set_controller_can_sleep();
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uint8_t data_input_ = 0;
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};
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};
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}
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}
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@ -25,10 +25,12 @@ void DiskIICard::perform_bus_operation(CPU::MOS6502::BusOperation operation, uin
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if(address < 0x100) {
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if(address < 0x100) {
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if(isReadOperation(operation)) *value = boot_[address];
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if(isReadOperation(operation)) *value = boot_[address];
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} else {
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} else {
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// TODO: data input really shouldn't happen only upon a write.
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diskii_.set_data_input(*value);
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const int disk_value = diskii_.read_address(address);
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if(isReadOperation(operation)) {
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if(isReadOperation(operation)) {
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*value = diskii_.get_register(address);
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if(disk_value != diskii_.DidNotLoad)
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} else {
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*value = static_cast<uint8_t>(disk_value);
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diskii_.set_register(address, *value);
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}
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}
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}
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}
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}
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}
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@ -405,9 +405,8 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface> class Co
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}
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}
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}
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}
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} else {
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} else {
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update_diskii();
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const int disk_value = diskii_.read_address(address);
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if(isReadOperation(operation)) *value = diskii_.get_register(address);
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if(isReadOperation(operation) && disk_value != diskii_.DidNotLoad) *value = static_cast<uint8_t>(disk_value);
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else diskii_.set_register(address, *value);
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}
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}
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break;
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break;
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}
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}
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@ -436,8 +435,13 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface> class Co
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tape_player_.run_for(Cycles(1));
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tape_player_.run_for(Cycles(1));
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switch(disk_interface) {
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switch(disk_interface) {
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default: break;
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default: break;
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case Analyser::Static::Oric::Target::DiskInterface::Microdisc: microdisc_.run_for(Cycles(8)); break;
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case Analyser::Static::Oric::Target::DiskInterface::Microdisc:
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case Analyser::Static::Oric::Target::DiskInterface::Pravetz: cycles_since_diskii_update_ += 2; break;
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microdisc_.run_for(Cycles(8));
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break;
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case Analyser::Static::Oric::Target::DiskInterface::Pravetz:
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diskii_.set_data_input(*value);
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diskii_.run_for(Cycles(2));
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break;
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}
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}
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cycles_since_video_update_++;
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cycles_since_video_update_++;
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return Cycles(1);
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return Cycles(1);
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@ -446,7 +450,6 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface> class Co
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forceinline void flush() {
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forceinline void flush() {
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update_video();
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update_video();
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via_port_handler_.flush();
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via_port_handler_.flush();
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if(disk_interface == Analyser::Static::Oric::Target::DiskInterface::Pravetz) update_diskii();
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}
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}
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// to satisfy CRTMachine::Machine
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// to satisfy CRTMachine::Machine
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@ -605,10 +608,10 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface> class Co
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Apple::DiskII diskii_;
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Apple::DiskII diskii_;
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std::vector<uint8_t> pravetz_rom_;
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std::vector<uint8_t> pravetz_rom_;
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std::size_t pravetz_rom_base_pointer_ = 0;
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std::size_t pravetz_rom_base_pointer_ = 0;
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Cycles cycles_since_diskii_update_;
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// Cycles cycles_since_diskii_update_;
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void update_diskii() {
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// void update_diskii() {
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diskii_.run_for(cycles_since_diskii_update_.flush());
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// diskii_.run_for(cycles_since_diskii_update_.flush());
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}
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// }
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// Overlay RAM
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// Overlay RAM
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uint16_t ram_top_ = basic_visible_ram_top_;
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uint16_t ram_top_ = basic_visible_ram_top_;
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@ -35,6 +35,9 @@ class AppleDSK: public DiskImage {
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HeadPosition get_maximum_head_position() override;
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HeadPosition get_maximum_head_position() override;
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std::shared_ptr<Track> get_track_at_position(Track::Address address) override;
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std::shared_ptr<Track> get_track_at_position(Track::Address address) override;
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// TEST!
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bool get_is_read_only() override { return false; }
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private:
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private:
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Storage::FileHolder file_;
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Storage::FileHolder file_;
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int sectors_per_track_ = 16;
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int sectors_per_track_ = 16;
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