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https://github.com/TomHarte/CLK.git
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Attempts a full implementation of asynchronous write mode.
This commit is contained in:
Thomas Harte
parent
1d1e0d74f8
commit
7baad61746
@ -95,11 +95,11 @@ uint8_t IWM::read(int address) {
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Read write-handshake register:
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bits 0-5: reserved for future use (currently read as 1).
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bit 6: 1 = write state (cleared to 0 if a write underrun occurs).
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bit 7: 1 = write data buffer ready for data.
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bit 6: 1 = write state (0 = underrun has occurred; 1 = no underrun so far).
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bit 7: 1 = write data buffer ready for data (1 = ready; 0 = busy).
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*/
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LOG("Reading write handshake");
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return 0x1f | write_handshake_;
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// LOG("Reading write handshake: " << PADHEX(2) << (0x3f | write_handshake_));
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return 0x3f | write_handshake_;
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}
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return 0xff;
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@ -137,15 +137,8 @@ void IWM::write(int address, uint8_t input) {
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break;
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case Q7|Q6|ENABLE: // Write data register.
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LOG("Data register write");
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if(write_handshake_ & 0x80) {
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shift_register_ = input;
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output_bits_remaining_ = 8;
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} else {
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next_output_ = input;
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write_handshake_ &= ~0x80;
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}
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next_output_ = input;
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write_handshake_ &= ~0x80;
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break;
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}
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}
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@ -199,32 +192,9 @@ void IWM::access(int address) {
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} break;
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case Q6:
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case Q7: {
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const auto old_shift_mode = shift_mode_;
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switch(state_ & (Q6|Q7)) {
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default: shift_mode_ = ShiftMode::CheckingWriteProtect; break;
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case 0: shift_mode_ = ShiftMode::Reading; break;
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case Q7:
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// "The IWM is put into the write state by a transition from the write protect sense state to the
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// write load state".
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if(shift_mode_ == ShiftMode::CheckingWriteProtect) shift_mode_ = ShiftMode::Writing;
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break;
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}
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// LOG("Shift mode is now " << int(shift_mode_));
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if(drives_[active_drive_]) {
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if(old_shift_mode == ShiftMode::Writing && shift_mode_ != ShiftMode::Writing) {
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drives_[active_drive_]->end_writing();
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write_handshake_ = 0xc0;
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}
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if(old_shift_mode != ShiftMode::Writing && shift_mode_ == ShiftMode::Writing) {
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drives_[active_drive_]->begin_writing(Storage::Time(1, clock_rate_), false);
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}
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}
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} break;
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case Q7:
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select_shift_mode();
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break;
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}
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}
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}
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@ -283,45 +253,82 @@ void IWM::run_for(const Cycles cycles) {
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break;
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case ShiftMode::Writing:
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while(cycles_since_shift_ + integer_cycles >= bit_length_) {
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const auto cycles_until_write = cycles_since_shift_ + integer_cycles - bit_length_;
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drives_[active_drive_]->run_for(cycles_until_write);
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if(drives_[active_drive_]->is_writing()) {
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while(cycles_since_shift_ + integer_cycles >= bit_length_) {
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const auto cycles_until_write = bit_length_ - cycles_since_shift_;
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drives_[active_drive_]->run_for(cycles_until_write);
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drives_[active_drive_]->write_bit(shift_register_ & 0x80); // Is this correct?
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shift_register_ <<= 1;
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cycles_since_shift_ = Cycles(0);
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// Output a flux transition if the top bit is set.
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drives_[active_drive_]->write_bit(shift_register_ & 0x80);
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shift_register_ <<= 1;
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integer_cycles -= cycles_until_write.as_int();
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--output_bits_remaining_;
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integer_cycles -= cycles_until_write.as_int();
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cycles_since_shift_ = Cycles(0);
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if(!output_bits_remaining_) {
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if(!(write_handshake_ & 0x80)) {
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write_handshake_ |= 0x80;
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shift_register_ = next_output_;
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output_bits_remaining_ = 8;
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} else {
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write_handshake_ &= ~0x40;
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drives_[active_drive_]->end_writing();
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--output_bits_remaining_;
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if(!output_bits_remaining_) {
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if(!(write_handshake_ & 0x80)) {
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write_handshake_ |= 0x80;
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shift_register_ = next_output_;
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output_bits_remaining_ = 8;
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// LOG("Next byte: " << PADHEX(2) << int(shift_register_));
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} else {
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write_handshake_ &= ~0x40;
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drives_[active_drive_]->end_writing();
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printf("\n");
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LOG("Overrun; done.");
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select_shift_mode();
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}
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}
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}
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}
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cycles_since_shift_ = integer_cycles;
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cycles_since_shift_ = integer_cycles;
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if(integer_cycles) {
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drives_[active_drive_]->run_for(cycles_since_shift_);
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}
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} else {
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drives_[active_drive_]->run_for(cycles);
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}
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break;
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case ShiftMode::CheckingWriteProtect:
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if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
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while(--integer_cycles) {
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shift_register_ = (shift_register_ >> 1) | sense();
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}
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break;
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/* Deliberate fallthrough. */
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default:
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if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
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break;
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}
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}
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void IWM::select_shift_mode() {
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// Don't allow an ongoing write to be interrupted.
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if(shift_mode_ == ShiftMode::Writing && drives_[active_drive_] && drives_[active_drive_]->is_writing()) return;
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const auto old_shift_mode = shift_mode_;
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switch(state_ & (Q6|Q7)) {
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default: shift_mode_ = ShiftMode::CheckingWriteProtect; break;
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case 0: shift_mode_ = ShiftMode::Reading; break;
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case Q7:
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// "The IWM is put into the write state by a transition from the write protect sense state to the
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// write load state".
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if(shift_mode_ == ShiftMode::CheckingWriteProtect) shift_mode_ = ShiftMode::Writing;
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break;
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}
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// If writing mode just began, set the drive into write mode and cue up the first output byte.
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if(drives_[active_drive_] && old_shift_mode != ShiftMode::Writing && shift_mode_ == ShiftMode::Writing) {
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drives_[active_drive_]->begin_writing(Storage::Time(1, clock_rate_ / bit_length_.as_int()), false);
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shift_register_ = next_output_;
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write_handshake_ |= 0x80 | 0x40;
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output_bits_remaining_ = 8;
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LOG("Seeding output with " << PADHEX(2) << shift_register_);
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}
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}
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uint8_t IWM::sense() {
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return drives_[active_drive_] ? (drives_[active_drive_]->read() ? 0x80 : 0x00) : 0x80;
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}
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@ -340,6 +347,7 @@ void IWM::process_event(const Storage::Disk::Drive::Event &event) {
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void IWM::propose_shift(uint8_t bit) {
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// TODO: synchronous mode.
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// LOG("Shifting input");
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shift_register_ = uint8_t((shift_register_ << 1) | bit);
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if(shift_register_ & 0x80) {
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data_register_ = shift_register_;
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@ -87,7 +87,7 @@ class IWM:
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void set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference clocking) override;
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Cycles cycles_until_disable_;
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uint8_t write_handshake_ = 0xc0;
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uint8_t write_handshake_ = 0x80;
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void access(int address);
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@ -108,6 +108,7 @@ class IWM:
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} shift_mode_;
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uint8_t sense();
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void select_shift_mode();
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};
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