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Address bus load time is not + 1/2.

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This commit is contained in:
Thomas Harte
2021-04-18 18:41:24 -04:00
parent 704737144a
commit 7bac18bd65
1 changed files with 3 additions and 3 deletions
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6
Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp
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@@ -245,7 +245,7 @@ template<Model model> class ConcreteMachine:
// always occurs if it is in the $4000–$8000 range regardless of current // always occurs if it is in the $4000–$8000 range regardless of current
// memory mapping. // memory mapping.
HalfCycles delay; HalfCycles delay;
HalfCycles time = video_.time_since_flush() + HalfCycles(1); HalfCycles time = video_.time_since_flush();
if((address & 0xc000) == 0x4000) { if((address & 0xc000) == 0x4000) {
for(int c = 0; c < ((address & 1) ? 4 : 2); c++) { for(int c = 0; c < ((address & 1) ? 4 : 2); c++) {
@@ -269,7 +269,7 @@ template<Model model> class ConcreteMachine:
// These all start by loading the address bus, then set MREQ // These all start by loading the address bus, then set MREQ
// half a cycle later. // half a cycle later.
if(is_contended_[address >> 14]) { if(is_contended_[address >> 14]) {
const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1)); const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush());
advance(cycle.length + delay); advance(cycle.length + delay);
return delay; return delay;
@@ -284,7 +284,7 @@ template<Model model> class ConcreteMachine:
const auto half_cycles = cycle.length.as<int>(); const auto half_cycles = cycle.length.as<int>();
assert(!(half_cycles & 1)); assert(!(half_cycles & 1));
HalfCycles time = video_.time_since_flush() + HalfCycles(1); HalfCycles time = video_.time_since_flush();
HalfCycles delay; HalfCycles delay;
for(int c = 0; c < half_cycles; c += 2) { for(int c = 0; c < half_cycles; c += 2) {
const auto next_delay = video_.last_valid()->access_delay(time); const auto next_delay = video_.last_valid()->access_delay(time);