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Slightly clean up shift code.
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parent
0866caf934
commit
7de92a9457
@ -58,9 +58,11 @@ struct Executor {
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operand2 = registers_[fields.operand2()];
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operand2 = registers_[fields.operand2()];
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}
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}
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uint32_t shift_amount;
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// TODO: in C++20, a quick `if constexpr (requires` can eliminate the `allow_register` parameter.
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if constexpr (allow_register) {
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if constexpr (allow_register) {
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if(fields.shift_count_is_register()) {
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if(fields.shift_count_is_register()) {
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uint32_t shift_amount;
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// "When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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// of the PC alone, with the PSR bits replaced by zeroes. ...
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//
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//
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@ -77,17 +79,14 @@ struct Executor {
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// A register shift amount of 0 has a different meaning than an in-instruction
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// A register shift amount of 0 has a different meaning than an in-instruction
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// shift amount of 0.
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// shift amount of 0.
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if(!shift_amount) {
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if(shift_amount) {
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shift<set_carry>(fields.shift_type(), operand2, shift_amount, rotate_carry);
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}
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return operand2;
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return operand2;
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}
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}
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} else {
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shift_amount = fields.shift_amount();
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}
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} else {
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shift_amount = fields.shift_amount();
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}
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}
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shift<set_carry>(fields.shift_type(), operand2, shift_amount, rotate_carry);
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shift<set_carry>(fields.shift_type(), operand2, fields.shift_amount(), rotate_carry);
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return operand2;
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return operand2;
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}
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}
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@ -306,15 +305,6 @@ struct Executor {
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// TODO: resolve uncertainty.
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// TODO: resolve uncertainty.
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constexpr bool should_write_back = !flags.pre_index() || flags.write_back_address();
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constexpr bool should_write_back = !flags.pre_index() || flags.write_back_address();
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// STR: update prior to write.
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// if constexpr (should_write_back && flags.operation() == SingleDataTransferFlags::Operation::STR) {
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// if(transfer.base() == 15) {
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// registers_.set_pc(offsetted_address);
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// } else {
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// registers_[transfer.base()] = offsetted_address;
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// }
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// }
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// "... post-indexed data transfers always write back the modified base. The only use of the [write-back address]
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// "... post-indexed data transfers always write back the modified base. The only use of the [write-back address]
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// bit in a post-indexed data transfer is in non-user mode code, where setting the W bit forces the /TRANS pin
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// bit in a post-indexed data transfer is in non-user mode code, where setting the W bit forces the /TRANS pin
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// to go LOW for the transfer"
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// to go LOW for the transfer"
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@ -375,10 +365,6 @@ struct Executor {
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}
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}
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}
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}
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// LDR: write back after load, only if original wasn't overwritten.
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// if constexpr (should_write_back && flags.operation() == SingleDataTransferFlags::Operation::LDR) {
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// if(transfer.base() != transfer.destination()) {
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if constexpr (should_write_back) {
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if constexpr (should_write_back) {
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// Empirically: I think writeback occurs before the access, so shouldn't overwrite on a load.
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// Empirically: I think writeback occurs before the access, so shouldn't overwrite on a load.
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if(flags.operation() == SingleDataTransferFlags::Operation::STR || transfer.base() != transfer.destination()) {
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if(flags.operation() == SingleDataTransferFlags::Operation::STR || transfer.base() != transfer.destination()) {
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